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| plls with i ntegrated vco - s m t 1 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z functional d iagram features ? r f bandwidth: 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z ? maximum phase d etector r ate 100 m h z ? ultra low phase n oise -110 dbc/ h z in band t yp. ? figure of merit (fom) -227 dbc/ h z ? <180 fs r m s jitter ? 24-bit s tep s ize, r esolution 3 h z typ ? e xact frequency mode ? built in d igital s elf t est ? 40 lead 6x6 mm s m t package: 36 mm 2 t ypical a pplications ? cellular/4 g , w imax i nfrastructure ? r epeaters and femtocells ? communications t est e quipment ? c at v e quipment ? phased a rray a pplications ? dds r eplacement ? very h igh d ata r ate r adios ? t unable r eference s ource for s purious- free performance for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com
plls with i ntegrated vco - s m t 2 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z g eneral d escription t he h mc834lp6 ge is a low noise, wide band, fractional- n phase-locked-loop (pll) that features an integrated voltage controlled oscillator (vco) with a fundamental frequency of 2800 m h z - 4200 m h z, and an integrated vco output d ivider (divide by 1/2/4/6.../60/62) and doubler, that together allow the h mc834lp6 ge to generate frequencies from 45 m h z to 1050 m h z, from 1400 m h z to 2100 m h z, from 2800 m h z to 4200 m h z, and from 5600 m h z to 8400 m h z. t he integrated phase d etector (p d ) and delta-sigma modulator, capable of operating at up to 100 m h z, permit wider loop-bandwidths with excellent spectral performance. t he h mc834lp6 ge features industry leading phase noise and spurious performance, across all frequencies, that enable it to minimize blocker effects, and improve receiver sensitivity and transmitter spectral purity. t he superior noise foor (< -170 dbc/ h z) makes the h mc834lp6 ge an ideal source for a variety of applications - such as; lo for r f mixers, a clock source for high-frequency data-converters, or a tunable reference source for ultra-low spurious applications. a dditional features of the h mc834lp6 ge include r f output power control from 0 to 6 db (~2 db steps), output mute function, and a delta-sigma modulator e xact frequency mode which enables users to generate output frequencies with 0 h z frequency error. parameter condition min. t yp. max. units rf output characteristics output frequency band 1 45 1050 m hz band 2 1400 2100 m hz band 3 2800 4200 mhz band 4 5600 8400 m hz vco frequency at pll i nput 2800 4200 m hz r f output frequency at f vco 2800 4200 m hz output power r f output power at f vco = 4000 m h z a cross a ll frequencies see figure 9 s ingle-ended power broadband matched i nternally [1] -2 0.5 2 dbm output power control ~2 db s teps 6 7. 5 db r f output power at f vco = 6000 m h z a cross a ll frequencies see figure 9 s ingle-ended power broadband matched i nternally [1] -11 -9 -7 dbm r f output power at f vco = 8000 m h z a cross a ll frequencies see figure 9 s ingle-ended power broadband matched i nternally [1] -13.5 -11 -8.5 dbm harmonics for fundamental mode fo mode at 4000 m h z 2nd / 3rd / 4th -25/-29/-38 dbc fo/2 mode at 4000 m h z/2 = 2 gh z 2nd / 3rd / 4th -25/-24/-35 dbc fo/30 mode at 2800 m h z/28 = 100 m h z 2nd / 3rd / 4th -20/-10/-26 dbc fo/62 mode at 2800 m h z/62 = 45 m h z 2nd / 3rd / 4th -14/-8/-21 dbc e lectrical specifcations vpp c p, v ddl s, v cc 1, v cc 2 = 5 v; r v dd , a v dd , d v dd 3v, v cc p d , v cch f, v cc ps = 3.3 v min and max specifed across t emp -40 c to +85 c [1] measured single-ended. a dditional 3 db possible with differential outputs. [2] measured with 100 external termination. s ee h ittite pll w/ i ntegraged vcos operating g uide r eference i nput s tage section for more details. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 3 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z parameter condition min. t yp. max. units harmonics in doubler mode 2fo mode at 5600 m h z 1/2 / 3rd / 4th/5th -10/-22/-25/-35 dbc vco output divider vco r f d ivider r ange 1,2,4,6,8,...,62 1 62 pll rf divider characteristics 19-bit n - d ivider r ange ( i nteger) max = 2 19 - 1 16 524,287 19-bit n - d ivider r ange (fractional) fractional nominal divide ratio varies (-3 / +4) dynamically max 20 524,283 ref input characteristics max r ef i nput frequency 350 m hz r ef i nput voltage a c coupled [2] 1 2 3.3 vp-p r ef i nput capacitance 5 pf 14-bit r - d ivider r ange 1 16,383 phase detector (pd) [3] p d frequency fractional mode b [4] dc 100 m hz p d frequency fractional mode a (and r egister 6 [17:16] = 11) dc 80 m hz p d frequency i nteger mode dc 125 m hz charge pump output current 0.02 2.54 ma charge pump g ain s tep s ize 20 a p d /charge pump ss b phase n oise 50 m h z r ef, i nput r eferred 1 k h z -143 dbc/ hz 10 k h z a dd 1 db for fractional -150 dbc/ hz 100 k h z a dd 3 db for fractional -153 dbc/ hz logic inputs vsw 40 50 60 % dv dd logic outputs vo h output h igh voltage dv dd v vol output low voltage 0 v output i mpedance 100 200 maximum load current 1.5 ma power supply voltages 3.3 v s upplies a v dd , vcc h f, vccp s , vccp d , r v dd , d v dd 3.0 3.3 3.5 v 5 v s upplies vppcp, v dd l s , vcc1, vcc2 4.8 5 5.2 v power supply currents +5 v a nalog charge pump vppcp, v dd ls 8 ma e lectrical specifcations (continued) [3] s lew rate of greater or equal to 0.5 ns/v is recommended, see pll with i ntegrated r f vcos operating g uide for more details. frequency is guaranteed across process voltage and temperature from -40 c to +85 c. [4] t his maximum phase detector frequency can only be achieved if the minimum n value is respected. eg. i n the case of fractional feedback mode, the maximum pf d rate = fvco/20 or 100 m h z, whichever is less. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 4 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z e lectrical specifcations (continued) parameter condition min. t yp. max. units +5 v vco core and vco buffer fo/1 mode vcc2 105 ma fo/ n mode vcc2 80 ma +5 v vco d ivider and r f/pll buffer s ingle- e nded output mode fo/1 mode vcc1 25 ma d ifferential output mode fo/1 mode vcc1 40 ma s ingle- e nded output mode fo/ n mode vcc1 80 100 ma d ifferential output mode fo/ n mode vcc1 95 115 ma +3.3 v a v dd , vcc h f, vccp s , vccp d , r v dd , d v dd 3v 52 ma power d own - crystal off r eg 01h=0, crystal n ot clocked 10 a power d own - crystal on, 100 m h z r eg01h =0, crystal clocked 100 m h z 5 ma power on reset t ypical r eset voltage on d v dd 700 mv min d v dd voltage for n o r eset 1.5 v power on r eset d elay 250 s vco open loop phase noise at fo @ 4 ghz 10 k h z offset -78 dbc/ hz 100 k h z offset -108 dbc/ hz 1 m h z offset -134.5 dbc/ hz 10 m h z offset -156 dbc/ hz 100 m h z offset -171 dbc/ hz vco open loop phase noise at fo @ 4 ghz/2 = 2 ghz 10 k h z offset -83 dbc/ hz 100 k h z offset -113 dbc/ hz 1 m h z offset -139.5 dbc/ hz 10 m h z offset -165.5 dbc/ hz 100 m h z offset -167 dbc/ hz vco open loop phase noise at fo @ 2.8 ghz/28 = 100 mhz 10 k h z offset -111 dbc/ hz 100 k h z offset -141 dbc/ hz 1 m h z offset -163.5 dbc/ hz 10 m h z offset -170 dbc/ hz 100 m h z offset -173 dbc/ hz vco open loop phase noise at 2fo @ 5.6 ghz 10 k h z offset -77 dbc/ hz 100 k h z offset -107 dbc/ hz 1 m h z offset -132 dbc/ hz 10 m h z offset -154 dbc/ hz 100 m h z offset -162 dbc/ hz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 5 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z parameter condition min. t yp. max. units vco open loop phase noise at 2fo @ 8 ghz 10 k h z offset -70 dbc/ hz 100 k h z offset -100 dbc/ hz 1 m h z offset -127 dbc/ hz 10 m h z offset -149 dbc/ hz 100 m h z offset -162 dbc/ hz figure of merit floor i nteger mode n ormalized to 1 h z -230 dbc/ hz floor fractional mode n ormalized to 1 h z -227 dbc/ hz flicker (both modes) n ormalized to 1 h z -268 dbc/ hz vco characteristics vco t uning s ensitivity at 4053 m h z measured at 2.5 v 15 m h z/v vco t uning s ensitivity at 3777 m h z measured at 2.5 v 13 m h z/v vco t uning s ensitivity at 3411 m h z measured at 2.5 v 12 m h z/v vco t uning s ensitivity at 2943 m h z measured at 2.5 v 11. 5 m h z/v vco s upply pushing measured at 2.5 v 2 m h z/v for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 6 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 1. t ypical c losed l oop i nteger phase n oise [loop filter confguration table] figure 5. t ypical v co sensitivity -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 fout 3600 mhz, loop bw 130 khz, rms jitter 136 fs fout 5600 mhz, loop bw 130 khz, rms jitter 116 fs fout 8300 mhz, loop bw 130 khz, rms jitter 212 fs fout 3600 mhz, loop bw 250 khz, rms jitter 86 fs fout 5600 mhz, loop bw 250 khz, rms jitter 76 fs fout 8300 mhz, loop bw 250 khz, rms jitter 98 fs phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 10 3 10 4 10 5 10 6 10 7 10 8 4053 mhz 3777 mhz 3411 mhz 2943 mhz offset (hz) phase noise (dbc/hz) figure 2. t ypical c losed l oop fractional phase n oise [loop filter confguration table] figure 3. free r unning phase noise at f0 figure 4. free r unning v co phase n oise vs. t emperature 0 1 2 3 4 5 2700 2900 3100 3300 3500 3700 3900 4100 4300 tune voltage after calibration (v) vco frequency(mhz) fmin fmax -180 -160 -140 -120 -100 -80 -60 10 3 10 4 10 5 10 6 10 7 10 8 fout 3605 mhz, loop bw 130 khz, rms jitter 145 fs fout 5605 mhz, loop bw 130 khz, rms jitter 123 fs fout 8305 mhz, loop bw 130 khz, rms jitter 227 fs fout 3605 mhz, loop bw 250 khz, rms jitter 110 fs fout 5605 mhz, loop bw 250 khz, rms jitter 95 fs fout 8305 mhz, loop bw 250 khz, rms jitter 112 fs offset (hz) phase noise (dbc/hz) 0 10 20 30 40 50 60 70 012345 4053 mhz at 2.5v, tuning cap 7 3777 mhz at 2.5v, tuning cap 7 3411 mhz at 2.5v, tuning cap 15 2943 mhz at 2.5v, tuning cap 15 tuning voltage (v) kvco (mhz/v) figure 6. t ypical t uning voltage a fter c alibration at f0 -180 -160 -140 -120 -100 -80 10 100 1000 10000 27c -40c 85c phase noise (dbc/hz) frequency (mhz) 100 mhz offset 1 mhz offset 100 khz offset for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 7 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 7. i ntegrated r ms jitter [1] [1] r m s jitter data is measured in fractional mode with 250 k h z loop bandwidth using 100 m h z reference, p d 50 m h z. i ntegration bandwidth from 1 k h z to 100 m h z. [2] measured from a 50 source with a 100 external resistor termination. s ee pll with i ntegrated r f vcos operating g uide r eference i nput s tage section for more details. full fom performance up to maximum 3.3 vpp input voltage. [3] measured from a 50 source with a 100 external resistor termination. s ee pll with i ntegrated r f vcos operating g uide r eference i nput s tage section for more details. full fom performance up to maximum 3.3 vpp input voltage. 40 60 80 100 120 140 160 180 200 10 100 1000 10000 -40c 27c 85c rms jitter (fs) frequency (mhz) -240 -230 -220 -210 -200 10 2 10 3 10 4 10 5 10 6 normalized phase noise (dbc/hz) frequency offset (hz) fom floor fom 1/f noise typ fom vs offset figure 8. figure of merit figure 9. t ypical o utput power vs. t emperature, maximum gain figure 10. rf output r eturn loss -235 -230 -225 -220 -215 -15 -10 -5 0 5 10 14 mhz sq 25 mhz sq 50 mhz sq 100 mhz sq floor fom (dbc/hz) reference power (dbm) 100 mhz 14 mhz 50 mhz 25 mhz figure 12. r eference i nput sensitivity, square w ave, 50 [2] -15 -10 -5 0 5 10 0 1000 2000 3000 4000 5000 6000 7000 8000 27 c -40 c 85 c output power (dbm) offset (mhz) figure 11. r eference i nput sensitivity sinusoid w ave, 50 [3] -235 -230 -225 -220 -215 -210 -205 -200 -20 -15 -10 -5 0 5 reference power (dbm) floor fom (dbc/hz) 14 mhz 25 mhz 50 mhz 100 mhz -30 -25 -20 -15 -10 -5 0 100 1000 10000 frequency (mhz) return loss(db) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 8 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 13. i nteger boundary spur at 3600.2 m h z [4] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) [4] fractional mode mode b, i nteger boundary s pur, loop filter bandwidth 130 k h z, re f in 100 m h z, 50 m h z p d [5] re f in 100 m h z, 50 m h z p d , output d ivider 4 s elected, loop filter bandwidth 130 k h z, channel s pacing 100 k h z [6] e xact frequency mode, re f in 100 m h z, 50 m h z p d , output d ivider 2 s elected, loop filter bandwidth = 130 k h z, channel s pacing = 100 k h z [7] e xact frequency mode, channel s pacing 100 k h z, r f out = 3951 m h z, re f in 100 m h z, 50 m h z p d , output d ivider 1 selected, loop filter bandwidth 130 k h z, [8] fractional mode b, r f out 3591 m h z, re f in 100 m h z, 50 m h z p d , output d ivider 1 selected, loop filter bandwidth 130 k h z. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 14. i nteger boundary spur at 8300.8 m h z [4] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 15. i nteger- n , e xact frequency mode on , performance at 900 m h z [5] figure 16. fractional- n , e xact frequency mode on , performance at 1813.5 m h z [6] figure 17. fractional- n , e xact frequency mode on , performance at 3591 m h z [7] -180 -160 -140 -120 -100 -80 -60 -40 -20 0 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 18. fractional- n , e xact frequency mode o ff, performance at 3591 m h z [8] for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 9 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z loop filter bw (k h z) c1 (pf) c2 (nf) c3 (pf) c4 (pf) r 2 (k) r 3 (k) r 4 (k) loop filter d esign 130 100 8.2 120 120 1 1.2 1.2 250 150 3.3 18 18 2.2 1 1 l oop filter c onfguration t able figure 19. w orst spur, fixed 50 m h z r eference, o utput freq. = 3900.1 m h z [9] -180 -160 -140 -120 -100 -80 -60 -40 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 20. w orst spur, t unable r eference 47.5 m h z, o utput frequency = 3900.1 m h z [9] -180 -144 -108 -72 -36 0 10 2 10 3 10 4 10 5 10 6 10 7 10 8 phase noise (dbc/hz) offset (hz) figure 21. w orst spur, fixed vs. t unable r eference [10] -110 -100 -90 -80 -70 -60 -50 3.9ghz +10 3 hz 3.9ghz +10 4 hz 3.9ghz +10 5 hz 3.9ghz +10 6 hz 3.9ghz +10 7 hz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency [9] capability of h mc834lp6 ge to generate low frequencies (as low as 45 m h z), enables the h mc834lp6 ge to be used as a tunable reference source into another h ittite pll. t his maximizes spur performance of h ittite plls. please see h mc834lp6 ge a pplication i nformation for more information. [10] t he graph is generated by observing, and plotting, the magnitude of only the worst spur (largest magnitude), at any offset, at each output frequency, while using a fxed 50 m h z reference and a tunable reference tuned to 47.5 m h z. s ee h mc834lp6 ge a pplication i nformation for more details. [11] phase noise performance of the h mc834lp6 ge when used as a tunable reference source. h mc834lp6 ge is operating at 4.2 gh z/42, 4.2 gh z/56, and 2.8 gh z/62 for the 100 m h z, 75 m h z, and 45.16129 m h z curves respectively, using a second order loop flter with 230 k h z bandwidth. figure 22. l ow frequency performance [11] -170 -160 -150 -140 -130 -120 10 2 10 3 10 4 10 5 10 6 10 7 10 8 carrier frequency 45.16129 mhz carrier frequency = 75 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (hz) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 10 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z pin d escriptions pin n umber function d escription 1 av dd d c power s upply for analog circuitry. 2, 5, 6, 8, 9, 11 - 14, 18 - 22, 24, 26, 29, 34, 37, 38 n /c t he pins are not connected internally; however, all data shown herein was measured with these pins connected to r f/ d c ground externally. 3 vppcp power s upply for charge pump analog section 4 cp charge pump output 7 v dd l s power s upply for the charge pump digital section 10 rv dd r eference s upply 15 x re fp r eference oscillator i nput 16 dv dd 3v d c power s upply for d igital (cmo s ) circuitry 17 c en chip e nable. connect to logic high for normal operation. 23 v tu ne vco varactor. t uning port i nput. 25 vcc2 vco a nalog s upply 2 27 vcc1 vco a nalog s upply 1 28 r f_ n r f n egative output (on in differential and single-ended confguration) 30 sen pll s erial port e nable (cmo s ) logic i nput 31 sdi pll s erial port d ata (cmo s ) logic i nput 32 s ck pll s erial port clock (cmo s ) logic i nput 33 ld _ sd o lock d etect, or s erial d ata, or g eneral purpose (cmo s ) logic output ( g po) 35 vcc hf d c power s upply for a nalog circuitry 36 vccp s d c power s upply for a nalog prescaler 39 vccp d d c power s upply for phase d etector 40 b ias e xternal bypass decoupling for precision bias circuits. n ote: 1.920v 20mv reference voltage (b ias ) is generated internally and cannot drive an external load. must be measured with 10 g meter such as a gilent 34410 a , normal 10m d vm will read erroneously. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 11 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z o utline d rawing part n umber package body material lead finish m s l r ating package marking [1] h mc834lp6 ge r o hs -compliant low s tress i njection molded plastic 100% matte s n m s l1 h 834 xxxx [1] 4- d igit lot number xxxx package i nformation n o tes : 1. p a ck age bo d y m ateria l: lo w stress in j ec ti o n mol ded pl asti c si l i c a and si l i co n i mp regnated . 2. l ead and gr ou nd p add l e m ateria l: copp er a lloy. 3. l ead and gr ou nd p add l e pl ating : 100% m atte tin . 4. di m ensi o ns are in in c hes [m i ll i m eters ]. 5. l ead s p a c ing t ol eran c e is n o n -cumul ati v e . 6. p ad bu rr l ength sha ll b e 0.15mm m a x. p ad bu rr height sha ll b e 0.25mm ma x. 7. p a ck age war p sha ll n ot e xc eed 0.05mm. 8. a ll gr ou nd l eads and gr ou nd p add l e mu st b e s ol dered t o pcb r f gr ou nd . 9. re f er to hittite a ppl i c ati o n n o te fo r s u ggested pcb l and p attern . a bsolute maximum r atings a v dd , r v dd , d v dd 3v, vccp d , vcc h f, vccp s -0.3v to +3.6v vppcp, v dd l s , vcc1, vcc2 -0.3v to +5.5v operating t emperature -40 c to +85c s torage t emperature -65 c to 150c maximum junction t emperature 125 c t hermal r esistance ( r th ) (junction to ground paddle) 20 c/ w r efow s oldering peak t emperature 260c t ime at peak t emperature 40 sec esd s ensitivity ( h bm) class 1b s tresses above those listed under a bsolute maximum r atings may cause permanent damage to the device. t his is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specifcation is not implied. e xposure to absolute maximum rating conditions for extended periods may affect device reliability. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 12 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z e valuation p c b schematic t he circuit board used in the application should use r f circuit design techniques. s ignal lines should have 50 ohm impedance while the package ground leads and exposed paddle should be connected directly to the ground plane similar to that shown. a sufficient number of via holes should be used to connect the top and bottom ground planes. t he evaluation circuit board shown is available from h ittite upon request. to view this e valuation pcb s chematic please visit www.hittite.com and choose HMC834LP6GE from the search by part number pull down menu to view the product splash page. e valuation p c b i tem contents part n umber e valuation pcb only h mc834lp6 ge e valuation pcb e v a l01- h mc834lp6 ge e valuation kit h mc834lp6 ge e valuation pcb u s b i nterface board 6 u s b a male to u s b b female cable c d r om (contains user manual, e valuation pcb s chematic, e valuation s oftware, h ittite pll d esign s oftware) e k it 01- h mc834lp6 ge e valuation o rder i nformation for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 13 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z h m c 834 l p6 ge a pplication i nformation large bandwidth, industry leading phase noise and spurious performance, excellent noise foor (<-170 dbc/ h z), coupled with a high level of integration make the h mc834lp6 ge ideal for a variety of applications; as an r f or i f stage lo, a clock source for high-frequency data-converters, or a tunable reference source for extremely low spurious applications (~ -100 dbc/ h z spurs). figure 23. HMC834LP6GE in a typical transmit chain figure 24. HMC834LP6GE in a typical receive chain figure 25. HMC834LP6GE used as a tunable reference for second HMC834LP6GE using the h mc834lp6 ge with a tunable reference as shown in figure 25 , it is possible to drastically improve spurious emissions performance across all frequencies. e xample shown in figure 21 graph shows that it is possible to have spurious emissions ~ -100 dbc/ h z across all frequencies. for more information about spurious emissions, how they are related to the reference frequency, and how to tune the reference frequency for optimal spurious performance please see the s purious performance section of h ittite pll w/ i ntegraged vcos operating g uide . n ote that at very low output frequencies < 100 m h z, harmonics increase due to small internal a c coupling. a pplications which are sensitive to harmonics may require external low pass fltering. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 14 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t he output of the h mc834lp6 ge is matched to 50 across all output frequencies from 45 m h z to 8400 m h z with gap. a s a result of the wideband 50 match, the output power of the h mc834lp6 ge decreases with increas - ing output frequency, as shown in figure 9 . i f required, it is possible to adjust the output stage gain setting of the h mc834lp6 ge (vco_ r eg 02h biases) at various operating frequencies in order to achieve a more constant output power level across the frequency operating range of the h mc834lp6 ge . a n example is shown in figure 26 . figure 26. reducing the output power variation of HMC834LP6GE across frequency by adjusting output stage gain control. i f a higher output power than that shown in figure 26 is required, it is possible to follow the HMC834LP6GE output stage with a simple amplifer such as h m c 311 s c70 e in order to achieve a constant and high output power level across the entire operating range of the HMC834LP6GE . o utput gain setting for o ptimal power flatness -20 -10 0 10 0 1000 2000 3000 4000 5000 6000 7000 8000 output power (dbm) output frequency (mhz) gain = 0 db gain = 9 db gain = 3 db divider output stage gain = 3 db (vco_reg02h[8] = 1) gain = 0 db for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 15 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.0 t heory of o peration h mc834lp6 ge is targeted for ultra low phase noise applications and has been designed with very low noise reference path, phase detector and charge pump. t he h mc834lp6 ge consists of the following functional blocks: 1. r eference path i nput buffers and r d ivider 2. vco path i nput buffer and multi-modulus n d ivider 3. ? fractional modulator 4. phase d etector 5. charge pump 6. s erial port with r ead w rite capability 7. g eneral purpose output ( g po) port 8. power on r eset circuit 9. vco s ubsystem 10. built- i n s elf t est features 1.1 v co subsystem t he h mc834lp6 ge contains a vco subsystem that can be confgured to operate in: ? fundamental frequency (fo) mode (2800 m h z to 4200 m h z). ? d ivide by n (fo/ n ), where n = 1,2,4,6,8...58,60,62 mode (45 m h z to 1400 m h z and 1400 m h z to 2100 m h z with gap). ? d oubler (2fo) mode (5600 m h z to 8400 m h z). a ll modes are vco register programmable as shown in figure 27 . one loop flter design can be used for the entire frequency of operation of the h mc834lp6 ge . figure 27. pll and vco subsystems for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 16 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.2 v co c alibration 1.2.1 v co a uto- c alibration ( a uto c al) h mc834lp6 ge uses a step tuned type vco. a simplifed step tuned vco is shown in figure 28 . a step tuned vco is a vco with a digitally selectable capacitor bank allowing the nominal center frequency of the vco to be adjusted or stepped by switching in/out vco tank capacitors. a more detailed view of a typical vco subsystem confguration is shown in figure 29 . a step tuned vco allows the user to center the vco on the required output frequency while keeping the varactor tuning voltage optimized near the mid-voltage tuning point of the h mc834lp6 ge s charge pump. t his enables the pll charge pump to tune the vco over the full range of operation with both a low tuning voltage and a low tuning sensitivity (kvco). t he vco switches are normally controlled automatically by the h mc834lp6 ge using the a uto-calibration feature. t he a uto-calibration feature is implemented in the internal state machine. i t manages the selection of the vco sub-band (capacitor selection) when a new frequency is programmed. t he vco switches may also be controlled directly via register r eg 05h for testing or for other special purpose operation. other control bits specifc to the vco are also sent via r eg 05h . figure 28. simplifed step tuned vco figure 29. HMC834LP6GE pll and vco subsystems t o use a step tuned vco in a closed loop, the vco must be calibrated such that the h mc834lp6 ge knows which switch position on the vco is optimum for the desired output frequency. t he h mc834lp6 ge supports a uto-calibration ( a utocal) of the step tuned vco. t he a utocal fxes the vco tuning voltage at the optimum mid-point of the charge pump output, then measures the free running vco frequency while searching for the setting which results in the free running output frequency that is closest to the for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 17 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z desired phase locked frequency. t his procedure results in a phase locked oscillator that locks over a very narrow voltage range on the varactor. a typical tuning curve for a step tuned vco is shown in figure 30 . n ote how the tuning voltage stays in a narrow range over a wide range of output frequencies. 0 1 2 3 4 5 920 960 1000 1040 1080 1120 1160 calibration frequency (mhz) tune voltage after calibration (v) 50mhz pfd, 500khz tuning steps, +25c 256 count calibration ,195khz resolution 31usec total cal time 0 15 31 figure 30. a typical 5-bit 32 switch vco tuning voltage after calibration t he calibration is normally run automatically once for every change of frequency. t his ensures optimum selection of vco switch settings vs. time and temperature. t he user does not normally have to be concerned about which switch setting is used for a given frequency as this is handled by the a utocal routine. t he accuracy required in the calibration affects the amount of time required to tune the vco. t he calibration routine searches for the best step setting that locks the vco at the current programmed frequency, and ensures that the vco will stay locked and perform well over its full temperature range without additional calibration, regardless of the temperature that the vco was calibrated at. a uto-calibration can also be disabled allowing manual vco tuning. r efer to section 1.2.2 for a description of manual tuning 1.2.1.1 a uto c al use of r eg05h a utocal transfers switch control data to the vco subsystem via r eg 05h . t he address of the vco subsystem in r eg 05h is not altered by the a utocal routine. t he address and id of the vco subsystem in r eg 05h must be set to the correct value before a utocal is executed. for more information see section 1.19 . 1.2.1.2 a uto-re l ock on l ock d etect failure i t is possible by setting r eg 07h [13] to have the vco subsystem automatically re-run the calibration routine and re-lock itself if lock d etect indicates an unlocked condition for any reason. w ith this option the system will attempt to re-lock only once. a uto-relock is recommended. 1.2.2 manual v co c alibration for fast frequency h opping i f it is desirable to switch frequencies very quickly it is possible to eliminate the a utocal time by calibrating the vco in advance and storing the switch number vs frequency information in the host. t his can be done by initially locking the pll with i ntegrated vco on each desired frequency using a utocal, then reading, and storing the vco switch settings selected. t he vco switch settings are available in r eg 10h [7:0] after every a utocal operation. t he host must then program the vco switch settings directly when changing frequencies. manual writes to the vco switches are executed immediately as are writes to the integer and fractional registers when a utocal is disabled. h ence frequency changes with manual control and a utocal disabled, requires a minimum of two serial port transfers to the pll, once to set the vco switches, and once to set the pll frequency. i f a utocal is disabled r eg 0 ah [11]=1 , the vco will update its registers with the value written via r eg 05h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 18 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z immediately. t he vco internal transfer requires 16 v s ck clock cycles after the completion of a write to r eg 05h . v s ck and the a utocal controller clock are equal to the input reference divided by 0, 4,16 or 32 as controlled by r eg 0 ah [14:13] . 1.2.2.1 r egisters required for frequency c hanges in fractional mode a large change of frequency, in fractional mode ( r eg 06h [11]=1 ), may require main s erial port writes to: 1. the integer register intg, r eg 03h (only required if the integer part changes) 2. the vco s p i register, r eg 05h ? required for manual control of vco if r eg 0 ah [11]=1 (autocal disabled) ? required to change the r f d ivider value if needed ( vco_ r eg 02h ) ? required to turn on/off the doubler mode if needed ( vco_ r eg 03h [0]) 3. the fractional register, r eg 04h . t he fractional register write triggers a utocal if r eg 0 ah [11]= 0 , and is loaded into the modulator automatically after a utocal runs. i f a utocal is disabled, r eg 0 ah [11]=1 , the fractional frequency change is loaded into the modulator immediately when the register is written with no adjustment to the vco. s mall steps in frequency in fractional mode, with a utocal enabled ( r eg 0 ah [11]= 0 ), usually only require a single write to the fractional register. w orst case, 5 main s erial port transfers to the h mc834lp6 ge could be required to change frequencies in fractional mode. i f the frequency step is small and the integer part of the frequency does not change, then the integer register is not changed. i n all cases, in fractional mode, it is necessary to write to the fractional register r eg 04h for frequency changes. 1.2.2.2 r egisters r equired for frequency c hanges in i nteger mode a change of frequency, in integer mode ( r eg 06h [11]= 0) , requires main s erial port writes to: 1. vco s p i register, r eg 05h ? required for manual control of vco if r eg 0 ah [11]=1 (autocal disabled) ? required to change the r f d ivider value if needed ( vco_ r eg 02h ) ? required to turn on/off the doubler mode if needed ( vco_ r eg 03h [0]) 2. the integer register r eg 03h . ? i n integer mode, an integer register write triggers a utocal if r eg 0 ah [11]= 0 , and is loaded into the prescaler automatically after a utocal runs. i f a utocal is disabled, r eg 0 ah [11]=1 , the integer frequency change is loaded into the prescaler immediately when written with no adjustment to the vco. n ormally changes to the integer register cause large steps in the vco frequency, hence the vco switch settings must be adjusted. a utocal enabled is the recommended method for integer mode frequency changes. i f a utocal is disabled ( r eg 0 ah [11]=1 ), a priori knowledge of the correct vco switch setting and the corresponding adjustment to the vco is required before executing the integer frequency change. 1.2.3 v co a uto c al on frequency c hange a ssuming r eg 0 ah [11]= 0 , the vco calibration starts automatically whenever a frequency change is requested. i f it is desired to rerun the a utocal routine for any reason, at the same frequency, simply rewrite the frequency change with the same value and the a utocal routine will execute again without changing fnal frequency. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 19 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.2.4 v co a uto c al t ime & a ccuracy t he vco frequency is counted for t mmt , the period of a single a utocal measurement cycle. t mmt = t xtal r 2 n ( e q 1) n is set by r eg 0 ah [2:0] and results in measurement periods which are multiples of the p d period, t xtal r . r is the reference path division ratio currently in use, r eg 02h t xtal is the period of the external reference (crystal) oscillator. t he vco a utocal counter will, on average, expect to register n counts, rounded down (foor) to the nearest integer, every p d cycle. n is the ratio of the target vco frequency, f vco , to the frequency of the p d , f pd , where n can be any rational number supported by the n divider. n is set by the integer ( n int = r eg 03h ) and fractional ( n frac = r eg 04h ) register contents n = n int + n frac / 2 24 ( e q 2) t he a utocal state machine and the data transfers to the internal vco subsystem s p i (v s p i ) run at the rate of the f s m clock, t fsm , where the f s m clock frequency cannot be greater than 50 m h z. t fsm = t xtal 2 m ( e q 3) m is 0, 2, 4 or 5 as determined by r eg 0 ah [14:13] t he expected number of vco counts, v, is given by v = foor (n 2 n ) ( e q 4) t he nominal vco frequency measured, f vcom , is given by f vcom = v f xtal / (2 n r) ( e q 5) where the worst case measurement error, f err , is: f err f pd / 2 n + 1 ( e q 6) figure 31. vco calibration a 5-bit step tuned vco, for example, nominally requires 5 measurements for calibration, worst case 6 measurements, and hence 7 v s p i data transfers of 20 clock cycles each. t he measurement has a programmable number of wait states, k, of 100 f s m cycles defned by r eg 0 ah [7:6] = k. h ence total calibration time, worst case, is given by: t cal = k100t fsm + 6t pd 2 n + 7 20t fsm ( e q 7) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 20 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z or equivalently t cal = t xtal (6r 2 n + (140+100k) 2 m ) where k = r eg 0 ah [7:6] decimal ( e q 8) for guaranteed hold of lock, across temperature extremes, the resolution should be better than 1/8 th the frequency step caused by a vco sub-band switch change. better resolution settings will show no improvement. 1.2.4.1 v co a uto c al e xample t he vco subsystem must satisfy the maximum f pd limited by the two following conditions: a. n 16 (f int ), n 20.0 (f frac ), where n = f vco/ f pd b. f pd 100 m h z s uppose the vco subsystem output frequency is to operate at 2.01 gh z. our example crystal frequency is f xtal = 50 mhz, r=1, and m=0 ( figure 31 ) , hence t fsm = 20 ns (50 m h z). n ote, when using a utocal, the maximum a utocal finite s tate machine (f s m) clock cannot exceed 60 m h z (see r eg 0 ah [14:13] ). t he f s m clock does not affect the accuracy of the measurement, it only affects the time to produce the result. t his same clock is used to clock the 16 bit vco serial port. i f time to change frequencies is not a concern, then one may set the calibration time for maximum accuracy, and therefore not be concerned with measurement resolution. using an input crystal of 50 m h z ( r =1 and fpd=50 m h z) the times and accuracies for calibration using ( e q 6) and ( e q 8) are shown in t able 1 . w here minimal tuning time is 1/8 th of the vco band spacing. a cross all vcos, a measurement resolution better than 800 k h z will produce correct results. s etting m = 0, n = 5, provides 781 k h z of resolution and adds 8.6 s of a utocal time to a normal frequency hop. once the a utocal sets the fnal switch value, 8.64 s after the frequency change command, the fractional register will be loaded, and the loop will lock with a normal transient predicted by the loop dynamics. h ence we can see in this example that a utocal typically adds about 8.6 s to the normal time to achieve frequ- ency lock. h ence, a utocal should be used for all but the most extreme frequency hopping requirements. t able 1. a uto c al e xample with f xtal = 50 m h z, r = 1, m = 0 control value reg0ah[2:0] n 2 n t mmt (s) t cal (s) f err max 0 0 1 0.02 4.92 25 m h z 1 1 2 0.04 5.04 12.5 m h z 2 2 4 0.08 5.28 6.25 m h z 3 3 8 0.16 5.76 3.125 m h z 4 5 32 0.64 8.64 781 k h z 5 6 64 1.28 12.48 390 k h z 6 7 128 2.56 20.16 195 k h z 7 8 256 5.12 35.52 98 k h z 1.2.5 v co o utput mute function t he output mute function enables the h mc834lp6 ge to disable the vco output while maintaining the pll and vco subsystems fully functional. t he mute function provides over 40 db of isolation throughout the operating range of the h mc834lp6 ge . t o mute the output of the h mc834lp6 ge , the following register writes are necessary: 1. vco_ r eg 03h [ 2] = 1, to place the vco subsystem in manual mode 2. vco_ r eg 01h [2] = 1, to disable the vco subsystem output buffer 3. vco_ r eg 01h [ 3] = 0, to disable the vco subsystem limiter. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 21 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z please note that the vco subsystem registers are not directly accessible. t hey are written to via pll r eg 05h . more information about vco subsystem s p i in section 1.19 . 1.3 v co built in t est with a uto c al t he frequency limits of the vco can be measured using the b ist features of the a utocal machine. t his is done by setting r eg 0 ah [10]=1 which freezes the vco switches in one position. vco switches may then be written manually, with the varactor biased at the nominal mid-rail voltage used for a utocal. for example to measure the vco maximum frequency use switch 0, written to the vco subsystem via r eg 05h =[000000000 0000 vco id ]. w here vco id = 000b. i f a utocal is enabled, ( r eg 0 ah [11] = 0), and a new frequency is written, a utocal will run, but with switches frozen. t he vco frequency error relative to the command frequency will be measured and results written to r e g 11h [19:0] where r e g 11h [19] is the sign bit. t he result will be written in terms of vco count error ( e q 4) . for example if the expected vco is 2 gh z, reference is 50 m h z, and n is 6, we expect to measure 2560 counts. i f we measure a difference of -5 counts in r e g 11h , then it means we actually measured 2555 counts. h ence the actual frequency of the vco is 5/2560 low, or 1.99609375 gh z, 1 count ~ 781 k h z. 1.4 spurious performance 1.4.1 i nteger o peration and r eference spurious t he vco always operates at an integer multiple of the p d frequency in an integer synthesizer. i n general, spurious signals originating from an integer synthesizer can only occur at multiples of the p d frequency. t hese unwanted outputs closest to the carrier are often simply referred to as reference sidebands. unwanted reference harmonics can also exist far from the carrier due to circuit isolation. s purs unrelated to the reference frequency must originate from outside sources. e xternal spurious sources can modulate the vco indirectly through power supplies, ground, or output ports, or bypass the loop flter due to poor isolation of the flter. i t can also simply add to the output of the pll. r eference spuri ous levels are typically below -100 dbc with a well designed board layout. a regulator with low noise and high power supply rejection, such as the h mc1060lp3 e , is recommended to minimize external spurious sources. r eference spurious levels of below -100 dbc require superb board isolation of power supplies, isolation of the vco from the digital switching of the synthesizer and isolation of the vco load from the synthesizer. t ypical board layout, regulator design, eval boards and application information are available for very low spurious operation. operation with lower levels of isolation in the application circuit board, from those rec - ommended by h ittite, can result in higher spurious levels. i f the application environment contains other interfering frequencies unrelated to the p d fre quency, and if the application isolation from the board layout and regulation are insufficient, the unwanted interfering frequencies will mix with the desired synthesizer output and cause additional spurious emissions. t he level of these emissions is dependant upon isolation and supply regulation or rejection (p srr ). 1.4.2 fractional o peration and spurious unlike an integer pll, spurious signals in a fractional pll can occur due to the fact that the vco operates at frequencies unrelated to the p d frequency. h ence intermodulation of the vco and the p d harmonics can cause spurious sidebands. s purious emissions are largest when the vco operates very close to an integer multiple of the p d . w hen the vco operates exactly at a harmonic of the p d then, no in-close mixing products are present. a s shown in figure 32 , interference is always present at multiples of the p d frequency, f pd , and the vco frequency, f vco . t he difference, , between the vco frequency and the nearest har monic of the reference, will create what are referred to as integer boundary spurs. d epending upon the mode of operation of for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 22 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z the synthesizer, higher order, lower power spurs may also occur at multiples of integer fractions (sub- harmonics) of the p d frequency. t hat is, fractional vco frequencies which are near nf pd + f pd d/m, where n, d and m are all integers and d plls with i ntegrated vco - s m t 23 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t he specifc level of charge pump offset current r eg 09h [20:14] is determined by this time offset, the comparison frequency and the charge pump current: ( ) ( ) ( ) 9 2.5 10 4 sec ,0.25 required cp offset min vco comparison cp cp t fi i ? ?? ? +? ? ? ? ?? ?? = where: t vco : is the rf period at the fractional prescaler input i cp : is the full scale current setting of the switching charge pump r eg 09h [6:0] r eg 09h [13:7] ( e q 9) operation with charge pump offset infuences the required confguration of the lock d etect function. r efer to the description of lock d etect function in section 1.11 . n ote that this calculation can be performed for the center frequency of the vco, and does not need refnement for small differences < 25 % in center frequencies. a nother factor in the spectral performance in fractional mode is the choice of the d elta- s igma modulator mode. mode a can offer better in-band spectral performance (inside the loop bandwidth) while mode b offers better out of band performance. s ee r eg 06h [3:2] for ds m mode selection. finally, all fractional synthesizers cre ate fractional spurs at some level. h ittite offers the lowest level fractional spurious in the indus try in an integrated solution. 1.4.2.2 spurious r elated to c hannel step size ( c hannel spurs) many fractional plls also create spurious emissions at offsets which are multiples of the channel step size. w e refer to these as channel s purs. i t is common in the industry to set the channel step size by use of the so-called modulus. for example, channel step size of 100 k h z requires a small modulus related to the step size, and often results in 100 k h z channel s purs. t he h mc834lp6 ge uses a large fxed modulus unrelated to the channel step size. a s a result, the h mc834lp6 ge has extremely low or unmeasurable channel s purs. i n addition e xact frequency mode ( 1.12.2.2 ) allows exact channel step size with no channel s purs. t he lack of channel s purs means that the h mc834lp6 ge has large regions of operation between i nteger boundaries with little or no spurs of any kind. large spurious free zones enable the h mc834lp6 ge to be used with a tunable reference, to effectively move the spur free zones and hence achieve spur-free operation at all frequencies. t he resulting pll is virtually spur-free at all frequencies. for more information see 1.4.2.3 . 1.4.2.3 spurious r eduction with t unable r eference s ection 1.4.2 discussed fractional mode i nteger boundary spurious caused by vco operation near reference harmonics. i t is possible, with h ittite fractional synthesizers, to virtually eliminate the integer boundary spurious at a given vco frequency by changing the frequency of the reference. t he reference frequency is normally generated by a crystal oscillator and is not tunable. h owever, h ittite wideband plls with i ntegrated vcos, including h mc834lp6 ge , can be used as a high-quality tunable reference source, as shown in figure 33 . figure 33. t unable reference source w ith the setup shown in figure 33 , the h mc834lp6 ge is capable of operating across all of its frequency range without sacrifcing phase noise, while virtually eliminating spurious emissions. optimum operation requires appropriate confguration of the two synthesizers to achieve this performance. h ittite apps-support can assist with the required algorithms for ultra-low spurious tunable reference applications. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 24 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a n h mc830lp6 ge tunable reference pll typically uses a high frequency crystal reference for best performance. phase noise from the mc830lp6 ge tunable reference output at 100 k h z offset varies typically from -145 dbc at 100 m h z output to -157 dbc at 25 m h z output. t his performance of h mc830lp6 ge as a tunable reference is equivalent to the phase noise of high performance crystal oscillators. figure 34. phase noise performance of the hmc833lp6ge -170 -160 -150 -140 -130 -120 0.1 1 10 100 1000 10000 100000 carrier frequency = 25 mhz carrier frequency = 55.55 mhz carrier frequency = 100 mhz phase noise (dbc/hz) offset (khz) when used with a tunable reference source. (hmc833lp6ge operating at 3 ghz/30, 3 ghz/54, and 1.55 ghz/62 for the 100 mhz, 55.55 mhz, and 25 mhz curves respectively.) w orst case spurious levels (largest spurs at any offset) of conventional fxed reference vs. a tunable reference can be compared by multiple individual phase noise measurements and summarized on a single plot vs. carrier frequency. for example, figure 35 shows the spectrum of a carrier operating at 2000.1 m h z with a 50 m h z fxed reference. t his case is 100 k h z away from an i nteger boundary (50 m h z x 40). w orst case spurious can be observed at 100 k h z offset and about -52 dbc in magnitude. figure 36 shows the same h mc834lp6 ge pll vco operating at the same 2000.1 m h z carrier frequency, using a tunable reference at 47.5 m h z generated by h mc830lp6 ge . w orst case spurious in this case can be observed at 5 m h z offset and about -100 dbc in magnitude. t he results of figure 35 and figure 36 show that the tunable reference source achieves 50 db better spurious performance, while maintaining essentially the same phase noise performance. -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (a) 2000.1 mhz carrier frequency worst spur at 100 khz offset at ~-52 dbc with 50 mhz crystal -180 -160 -140 -120 -100 -80 -60 -40 -20 0 0.1 1 10 100 1000 10000 100000 phase noise (dbc/hz) offset (khz) (b) 2000.1 mhz carrier frequency worst spur at 5 khz offset at -100 dbc with tunable crystal figure 35. HMC834LP6GE worst spur at any offset, fxed 50 mhz reference, output frequency = 2000.1 mhz figure 36. HMC834LP6GE worst spur at any offset, tunable reference (hmc830lp6ge), output frequency = 2000.1 mhz many spurious measurements, such as the ones in figure 35 and figure 36 can be summarized into a single plot of worst case spurious at any offset vs. carrier frequency as shown in figure 37 . a log frequency display relative to the 2000 m h z fxed reference i nteger boundary was used to emphasize the importance for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 25 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z of the loop bandwidth on spurious performance of the fxed reference case. t his technique clearly shows the logarithmic roll-off of the worst case spurious when operating near the i nteger boundary. i n this case the loop flter bandwidth of the h mc834lp6 ge was 100 k h z. figure 37. -120 -110 -100 -90 -80 -70 -60 -50 2ghz +1khz 2ghz +10khz 2ghz +100khz 2ghz +1000khz 2ghz +10000khz fixed 50 mhz reference tunable reference worst spur (dbc) output frequency (a) (b) largest observed spurious, at any offset, using a fxed 50 mhz reference source and a tunable reference source. for example worst case spurious operating at 2000.1 m h z (point ( a )) in figure 35 with a fxed 50 m h z reference) is represented by a single point in figure 37 (point ( a )) on the blue curve. s imilarly, worst case spurious from figure 36 with variable reference, operating at 2000.1 m h z is represented by a single point in figure 37 (point (b)) on the green curve. t he plot in figure 37 is generated by tuning the carrier frequency away from i nteger boundary and recording the worst case spurious, at any offset, at each operating frequency. figure 37 shows that the worst case spurious for the 50 m h z fxed reference case, is nearly constant between -51 dbc and -55 dbc when operating with a carrier frequency less than 100 k h z from the i nteger boundary (blue curve). i t also shows that the worst case spurious rolls off at about 25 db/decade relative to 1 loop bandwidth. for example, at an operating frequency of 2001 m h z (equivalent to 10 loop bandwidths offset) worst case spurious is -80 dbc. s imilarly, at an operating frequency of 2010 m h z (equivalent to 100 loop bandwidths) worst case spurious is -100 dbc. i n contrast, the green curve of figure 37 shows that the worst case spurious over the same operating frequency range, when using an h mc830lp6 ge tunable reference, is below -100 dbc at all operating frequencies! i n general all fractional plls have spurious when operating near i nteger boundaries. h igh performance tunable reference makes it possible to operate h mc834lp6 ge , virtually spur-free at all frequencies, with little or no degradation in phase noise. 1.5 i ntegrated phase n oise & jitter t he standard deviation of vco signal jitter may be estimated with a simple approximation if it is assumed that the locked vco has a constant phase noise, o | 2 ( f o ), at offsets less than the loop 3 db bandwidth and a 20 db per decade roll-off at greater offsets. t he simple locked vco phase noise approximation is shown on the left of figure 38 . for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 26 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 38. pll with integrated vco phase noise & jitter w ith this simplifcation the total integrated vco phase noise, o | 2 , in rads 2 in the linear form is given by o | 2 = o | 2 (f o ) b ( e q 10) where o | 2 (f o ) is the single sideband phase noise in rads 2 / h z inside the loop bandwidth, and b is the 3 db corner frequency of the closed loop pll t he integrated phase noise at the phase frequency detector, o | 2 pd is just scaled by n 2 /n 2 = o | 2 pd o | 2 ( e q 11) t he rms phase jitter of the vco in rads, o | , is just the square root of the phase noise integral. s ince the simple integral of ( e q 10) is just a product of constants, we can easily do the integral in the log domain. for example if the vco phase noise inside the loop is -100 dbc/ h z at 10 k h z offset and the loop bandwidth is 100 k h z, and the division ratio is 100, then the integrated phase noise at the phase frequency detector, in db, is given by: o | 2 = 10log ( o | 2 ( f o )b/ n 2 ) = -100 + 50 + 5 - 40 = -85 dbc pddb or equivalently, o | = 1 0 -85/20 = 53.6e-6 rads = 3.2e-3 degrees. w hile the phase noise reduces by a factor of 20log n after division to the reference, due to the increased period of the p d reference signal, the jitter is constant. t he rms jitter from the phase noise is then given by t jpn = t pd o | pd /2 ( e q 12) i n this example if the p d reference was 50 m h z, t pd = 20ns, and hence t jpn = 179 femto-sec. i t should be noted that this last expression is based upon a closed form integral of the entire spectrum of the oscillator phase noise. t his integral starts at d c. i t is common for real system to evaluate jitter over shorter intervals of time, hence the integral often starts at some fnite frequency offset and will produce a jitter that is less than that given by the full expression. finally real oscillators have noise foors that also contribute to jitter. t he phase noise of a white noise foor is a simple integral of noise foor density times bandwidth of interest to the system. t his additional noise power should be added to the expression of ( e q 16) to give a more accurate jitter number. d epending upon the bandwidth of the system in question this noise foor contribution may be an important factor. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 27 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.6 r eference i nput stage figure 39. reference path input stage t he reference buffer provides the path from an external reference source (generally crystal based) to the r divider, and eventually to the phase detector. t he buffer has two modes of operation controlled by r eg 08h [21]. h igh g ain ( r eg 08h [21] = 0), recommended below 200 m h z, and h igh frequency ( r eg 08h [21] = 1), for 200 to 350 m h z operation. t he buffer is internally d c biased, with 100 internal termination. for 50 match, an external 100 resistor to ground should be added, followed by an a c coupling capacitor (impedance < 1 ), then to the x re fp pin of the part. a t low frequencies, a relatively square reference is recommended to keep the input slew rate high. a t higher frequencies, a square or sinusoid can be used. t he following table shows the recommended operating regions for different reference frequencies. i f operating outside these regions the part will normally still operate, but with degraded reference path phase noise performance. minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1, the pulse width should be (2.5ns + 8 t ps ), where t ps is the period of the vco at the prescaler input. w hen r > 1 minimum pulse width is 2.5 ns. t able 2. r eference sensitivity t able s quare input s inusoidal input r eference input frequency (mhz) s lew > 0.5v/ns r ecommended s wing (vpp) r ecommended power r ange (dbm) r ecommended min max r ecommended min max < 10 yes 0.6 2.5 x x x 10 yes 0.6 2.5 x x x 25 yes 0.6 2.5 ok 8 15 50 yes 0.6 2.5 yes 6 15 100 yes 0.6 2.5 yes 5 15 150 ok 0.9 2.5 yes 4 12 200 ok 1. 2 2.5 yes 3 8 i nput referred phase noise of the pll when operating at 50 m h z is between -150 and -156 dbc/ h z at 10 k h z offset depending upon the mode of operation. t he input reference signal should be 10 db better than this foor to avoid deg radation of the pll noise contribution. i t should be noted that such low levels are only necessary if the pll is the dominant noise contributor and these levels are required for the system goals. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 28 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.7 r eference path r d ivider t he reference path r divider is based on a 14-bit counter and can divide input signals by values from 1 to 16,383 and is controlled by rdiv ( r eg 02h ). minimum pulse width at the reference buffer input is 2.5 ns. for best spur performance when r = 1, the pulse width should be (2.5 ns + 8 t ps), where t ps is the period of the vco at the prescaler input. w hen r > 1 minimum pulse width is 2.5 ns. 1.8 r f path n d ivider t he main r f path divider is capable of average divide ratios between 2 19 -5 (524,283) and 20 in fractional mode, and 2 19 -1 (524,287) to 16 in integer mode. t he vco frequency range divided by the minimum n divider value will place practical restrictions on the maximum usable p d frequency. for example a vco operating at 1.5 gh z in fractional mode with a minimum n divider value of 20 will have a maximum p d frequency of 75 m h z. 1.9 c harge pump & phase d etector t he phase detector (p d ) has two inputs, one from the reference path divider and one from the r f path divider. w hen in lock these two inputs are at the same average frequency and are fxed at a constant average phase offset with respect to each other. w e refer to the frequency of operation of the p d as f pd . most formulae related to step size, delta-sigma modulation, timers etc., are functions of the operating frequency of the p d , f pd . f pd is also referred to as the comparison frequency of the p d . t he p d compares the phase of the r f path signal with that of the reference path signal and controls the charge pump output current as a linear function of the phase difference between the two signals. t he output current varies linearly over a full 2 radians (360) of input phase difference. 1.10 phase d etector functions phase detector register r eg 0bh allows manual access to control special phase detector features. pd_up_en ( r eg 0bh [5]), if 0, masks the p d up output, which prevents the charge pump from pumping up.` pd_dn_en ( r eg 0bh [6]), if 0, masks the p d down output, which prevents the charge pump from pumping down. clearing both pd_up_en and pd_dn_en effectively tri-states the charge pump while leaving all other functions operating internally. p d force up r eg 0bh [9] = 1 and p d force dn r eg 0bh [10] = 1 allows the charge pump to be forced up or down respectively. t his will force the vco to the ends to the tuning range which can be useful in test of the vco. 1.11 phase d etector w indow based l ock d etect lock detect enable r eg 07h [3]=1 is a global enable for all lock detect functions. t he window based lock d etect circuit effectively measures the difference between the arrival of the reference and the divided vco signals at the p d . t he arrival time difference must consistently be less than the lock d etect window length, to declare lock. e ither signal may arrive frst, only the difference in arrival times is counted. 1.11.1 a nalog w indow l ock d etect t he lock detect window may be generated by either an analog one shot circuit or a digital one shot based upon an internal timer. s etting r eg 07h [6]=0 will result in a fxed, analog, nominal 10 ns window, as shown in figure 40 . t he analog window cannot be used if the p d rate is above 50 m h z, or if the offset is too large. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 29 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 40. normal lock detect window - integer mode, zero offset for example a 25 m h z p d rate with a 1 m a charge pump setting ( r eg 09h [6:0]= r eg 09h [13:7]= 32h) and 400 a offset down current ( r eg 09h [20:14]= 50h r eg 09h [22]= 1) , would have an offset of about 400/1000 = 40% of the p d period or about 16 ns. i n such an extreme case the divided vco would arrive 16 ns after the p d reference, and would always arrive outside of the 10 ns lock detect window. i n such a case the lock detect circuit would always read unlocked, even though the vco might be locked. w hen using the 10 ns analog lock detect window, with a 40 ns p d period, the offset must always be less than 25% of the charge pump setting, 20% to allow for tolerances. h ence a 1 m a charge pump setting can not use more than 200 a offset with a 25 m h z p d and an analog lock detect window. charge pump current, charge pump offset, phase detector rate and lock detect window are related. 1.11.2 d igital w indow l ock d etect s etting r eg 07h [6]=1 will result in a variable length lock detect window based upon an internal digital timer. t he timer period is set by the number of cycles of the internal l d clock as programmed by r eg 07h [9:7]. t he l d clock frequency is adjustable by r eg 07h [11:10]. t he l d clock signal can be viewed via the g po test pins. r efer 1.16 for details. 1.11.3 d eclaration of l ock wincnt_max in r eg 07h [2:0] defnes the number of consecutive counts of the divided vco that must land inside the lock detect window to declare lock. i f for example we set wincnt_max = 2048, then the vco arrival would have to occur inside the window 2048 times in a row to be declared locked, which would result in a lock d etect flag high. a single occurrence outside of the window will result in an out of lock, i.e. lock d etect flag low. once low, the lock d etect flag will stay low until the wincnt_max = 2048 condition is met again. t he lock d etect flag status is always readable in r eg 12h [1] , if locked = 1. lock d etect status is also output to the l d _ sd o pin if r eg 0fh [4:0]=1 . a gain, if locked, l d _ sd o will be high. s etting r eg 0fh [6]=0 will display the lock d etect flag on l d _ sd o except when a serial port read is requested, in which case the pin reverts temporarily to the s erial d ata out pin, and returns to the lock d etect flag after the read is completed. r efer to 1.11.5 for t iming of the lock d etect information. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 30 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.11.4 phase o ffset & fractional l inearity w hen operating in fractional mode the linearity of the charge pump and phase detector are much more critical than in integer mode. t he phase detector linearity is degraded when operating with zero phase offset. h ence in fractional mode it is necessary to offset the phase of the p d reference and the vco at the phase detector. i n such a case, for example with an offset delay, as shown in figure 41 , the vco arrival will always occur after the reference. t he lock detect circuit window may need to be adjusted to allow for the delay being used. for details see section d igital lock d etect with d igital w indow e xample . figure 41. lock detect window - fractional mode with offset 1.11.5 d igital l ock d etect with d igital w indow e xample t ypical d igital lock detect window widths are shown in t able 3 . lock d etect windows typically vary 10% vs voltage and 25% over temperature (-40c to +85c). t able 3. t ypical d igital l ock d etect w indow ld timer speed reg07[11:10] digital lock detect window nominal value 25% (ns) fastest 00 6.5 8 11 17 29 53 100 195 01 7 8.9 12.8 21 36 68 130 255 10 1.7 9.2 13.3 22 38 72 138 272 s lowest 11 7.6 10.2 15.4 26 47 88 172 338 l d t imer d ivide s etting r eg07[9:7] 0 1 2 3 4 5 6 7 l d t imer d ivide value 0.5 1 2 4 8 16 32 64 a s an example, in fractional mode, with a 50 m h z p d , with a charge pump gain of 2 m a and a d own leakage of -400 a ( r eg 09h [13:7] = 64h, r eg 09h [6:0] = 64h, r eg 09h [20:14] = 50h, r eg 09h [22] = 1), the average offset at the p d will be -0.400/2 = 0.2 of the p d period, or about 4 ns 25%. h ence, when in lock, the divided vco will arrive at the p d about 4 ns after the divided r eference. t he lock d etect w indow always starts on the arrival of the frst signal at the p d , in this case the r eference. t he lock d etect window must be longer than 4 ns + 25% and shorter than the period of the p d , in this example, 20 ns. a perfect lock d etect window would be the geometric mean or 9.8 ns. a comfortable solution of 12.8 ns with timer speed set at r eg 07h [11:10]=1 and t imer divider r eg 07h [9:7]=2 works well for the example p d frequency and charge pump offset setting. t olerance on the window is +25% at +85 c, -25% at -40 c. h ere 12.8 ns nominal window may extend by +25% at +85c to 16 ns, which is fne for a p d period of 20 ns. a lso the minimum window may shrink by 25% to 9.6 ns at -40c, which again works well for the worst case offset of 4.6 ns. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 31 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z figure 42. lock detect window example with 50 mhz pd and 3.9 ns vco offset t here is always a good solution for the lock detect window for a given operating point. t he user should understand however that one solution does not ft all operating points. i f charge pump offset or p d frequency are changed signifcantly then the lock detect window may need to be adjusted. 1.11.6 c ycle slip prevention ( c sp) w hen changing vco frequency and the vco is not yet locked to the reference, the instantaneous frequencies of the two p d inputs are different, and the phase difference of the two inputs at the p d varies rapidly over a range much greater than 2 radians. s ince the gain of the p d varies linearly with phase up to 2, the gain of a conventional p d will cycle from high gain, when the phase difference approaches a multiple of 2, to low gain, when the phase difference is slightly larger than a multiple of 0 radians. t he output current from the charge pump will cycle from maximum to minimum even though the vco has not yet reached its fnal frequency. t he charge on the loop flter small cap may actually discharge slightly during the low gain portion of the cycle. t his can make the vco frequency actually reverse temporarily during locking. t his phenomena is known as cycle slipping. cycle slipping causes the pull-in rate during the locking phase to vary cyclically. cycle s lipping increases the time to lock to a value greater than that predicted by normal small signal laplace analysis. t he synthesizer p d features an ability to reduce cycle slipping during acquisition. t he cycle s lip preven - tion (c s p) feature increases the p d gain during large phase errors. t he specifc phase error that triggers the momentary increase in p d gain is set via r eg 0bh [8:7] 1.11.7 c harge pump g ain a simplifed diagram of the charge pump is shown in figure 43 . charge pump up and d own gains are set by cp dn gain and cp up gain respectively ( r eg 09h [6:0] and r eg 09h [13:7]) . t he current gain of the pump in a mps/radian is equal to the gain setting of this register divided by 2. for example if both cp dn gain and cp up gain are set to 50d the output current of each pump will be 1 m a and the phase frequency detector gain k p = 1 m a /2 radians, or 159 a /rad. s ee section 1.4 for more information. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 32 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.11.8 c harge pump phase o ffset - fractional mode i n integer mode, the phase detector operates with zero offset. t he divided reference signal and the divided vco signal arrive at the phase detector inputs at the same time. i n fractional mode of operation, charge pump linearity and ultimately, phase noise, is much better if the vco and reference inputs are operated with a phase offset. a phase offset is implemented by adding a constant d c offset current at the output of the charge pump. d c offset may be added to the up or dn switching pumps using r eg 09h [21] or r eg 09h [22] . t he magnitude of the offset is controlled by r eg 09h [20:14], and can range from 0 to 635 a in steps of 5 a . d own offset is highly recommended in fractional mode of operation. i nteger mode of operation works best with zero offset. a s an example, a p d comparison of f pd = 50 m h z (20 ns period) with the main pump gain set at 2 m a , and a down ( dn ) offset of -385 a would represent a phase offset of about (-385/2000)*360 = -69 degrees. t his is equivalent to the divided vco arriving 3.8 ns after the reference at the p d input. i t is critical that phase offset be used in fractional mode. n ormally, down offsets larger than 3 ns are typical. i f the charge pump gain is changed, for example to compensate for changes in vco sensitivity, it is recommended to change the charge pump offset proportionally to maintain a constant phase offset. figure 43. charge pump gain & offset control 1.12 frequency t uning h mc834lp6 ge vco subsystem always operates in fundamental frequency of operation (2800 m h z to 4200 m h z). t he h mc834lp6 ge generates frequencies below its fundamental frequency (45 m h z to 2800 m h z) by tuning to the appropriate fundamental frequency and selecting the appropriate output d ivider setting (divide by 2/4/6.../60/62) in vco_ r eg 02h [5:0]. conversely the h mc834lp6 ge generates frequencies greater than its fundamental frequency (5600 m h z to 8400 m h z) by tuning to the appropriate fundamental frequency and enabling the doubler mode ( vco_ r eg 03h [0] = 1 ). t he h mc834lp6 ge automatically controls frequency tuning in the fundamental band of operation, for more information see 1.2.1 vco a uto-calibration ( a utocal) . t o tune to frequencies below the fundamental frequency range (<2800 m h z) it is required to tune the h mc834lp6 ge to the appropriate fundamental frequency, then select the appropriate output divider setting (divide by 2/4/6.../60/62) in vco_ r eg 02h [5:0]. s imilarly, to tune to frequencies above the fundamental frequency range (>4200 m h z) it is required to tune the h mc834lp6 ge to the appropriate fundamental frequency, and then enable the doubler mode of operation ( vco_ r eg 03h [0] = 1 ). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 33 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.1 i nteger mode t he h mc834lp6 ge is capable of operating in integer mode. for i nteger mode set the following registers a. d isable the fractional modulator, r eg 06h [11]= 0 b. bypass the modulator circuit, r eg 06h [7]=1 i n integer mode the vco step size is fxed to that of the p d frequency, f pd . i nteger mode typically has 3 db lower phase noise than fractional mode for a given p d operating frequency. i nteger mode, however, often requires a lower p d frequency to meet step size requirements. t he fractional mode advantage is that higher p d frequencies can be used, hence lower phase noise can often be realized in fractional mode. charge pump offset should be disabled in integer mode. 1.12.1.1 i nteger frequency t uning i n integer mode the digital ? modulator is shut off and the n ( r eg 03h ) divider may be programmed to any integer value in the range 16 to 2 19 -1. t o run in integer mode confgure r eg 06h as described, then program the integer portion of the frequency as explained by ( e q 13) , ignoring the fractional part. a. d isable the fractional modulator, r eg 06h [11] = 0 b. bypass the delta-sigma modulator r eg 06h [7] = 1 c. t o tune to frequencies (<2800 m h z), select the appropriate output divider value vco_ r eg 02h [5:0]. d. t o tune to frequencies (>4200 m h z), enable the doubler mode of operation ( vco_ r eg 03h [0] = 1). w riting to vco subsystem registers ( vco_ r eg 02h [5:0] and vco_ r eg 03h [0] in this case ) is accomplished indirectly through pll register 5 ( r eg 05h ). more information on communicating with the vco subsystem through pll r eg 05h is available in 1.19 vco s erial port i nterface ( s p i ) section. 1.12.2 fractional mode t he h mc834lp6 ge is placed in fractional mode by setting the following registers: a. e nable the fractional modulator, r eg 06h [11]=1 b. connect the delta sigma modulator in circuit, r eg 06h [7]=0 1.12.2.1 fractional frequency t uning t his is a generic example, with the goal of explaining how to program the output frequency. a ctual variables are dependant upon the reference in use. t he h mc834lp6 ge in fractional mode can achieve frequencies at fractional multiples of the reference. t he frequency of the h mc834lp6 ge , f vco , is given by f vco = ( n int + n frac ) = f int + f frac f xtal r ( e q 13) f out = f vco / k ( e q 14) w here: f out is the output frequency after any potential dividers or doublers. k is 0.5 for doubler, 1 for fundamental, or k = 1,2,4,6,58,60,62 according to the vco s ubsystem type n int is the integer division ratio, r eg 03h , an integer number between 20 and 524,284 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 34 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z n frac is the fractional part, from 0.0 to 0.99999..., n frac = r eg 04h /2 24 r is the reference path division ratio, r eg 02h f xtal is the frequency of the reference oscillator input f pd is the p d operating frequency, f xtal /r a s an example: f out 1402.5 m h z k 2 f vco 2,805 m hz f xtal = 50 m h z r = 1 f pd = 50 m h z n int = 56 n frac = 0.1 r eg 04h = round(0.1 x 2 24 ) = round(1677721.6) = 1677722 f vco = ( 56 + - ) = 2805 mhz + 1.92 hz error 1677722 2 24 50e6 1 ( e q 15) f out = = 1402.5 mhz + 0.596 hz error f vco 2 ( e q 16) i n this example the output frequency of 1402.5 m h z is achieved by programming the 19-bit binary value of 56d = 38h into intg_reg in r eg 03h , and the 24-bit binary value of 1677722d = 19999 a h into frac_reg in r eg 04h . t he 0.596 h z quantization error can be eliminated using the exact frequency mode if required. i n this example the output fundamental is divided by 2. s pecifc control of the output divider is required. s ee section 3.0 and description for more details. 1.12.2.2 e xact frequency t uning d ue to quantization effects, the absolute frequency precision of a fractional pll is normally limited by the number of bits in the fractional modulator. for example, a 24 bit fractional modulator has frequency resolution set by the phase detector (p d ) comparison rate divided by 2 24 . t he value 2 24 in the denominator is sometimes referred to as the modulus. h ittite plls use a fxed modulus which is a binary number. i n some types of fractional plls the modulus is variable, which allows exact frequency steps to be achieved with decimal step sizes. unfortunately small steps using small modulus values results in large spurious outputs at multiples of the modulus period (channel step size). for this reason h ittite plls use a large fxed modulus. n ormally, the step size is set by the size of the fxed modulus. i n the case of a 50 m h z p d rate, a modulus of 2 24 would result in a 2.98 h z step resolution, or 0.0596 ppm. i n some applications it is necessary to have exact frequency steps, and even an error of 3 h z cannot be tol erated. fractional plls are able to generate exact frequencies (with zero frequency error) if n can be exactly represented in binary (eg. n = 50.0,50.5,50.25,50.75 etc.). unfortunately, some common frequencies cannot be exactly represented. for example, n frac = 0.1 = 1/10 must be approximated as round((0.1 x 2 24 )/ 2 24 ) 0.100000024. a t f pd = 50 m h z this translates to 1.2 h z error. h ittites exact frequency mode addresses this issue, and can eliminate quantization error by programming the channel step size to f pd /10 in r eg 0ch to 10 (in this example). more generally, this feature can be used whenever the desired for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 35 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z frequency, f vco , can be exactly represented on a step plan where there are an integer number of steps (<2 14 ) across integer- n boundaries. mathematically, this situation is satisfed if: gcd gcd gcd 1 14 mod 0 where gcd( , ) 2 f pd pd vcok vco f f f f f and f ?? ?? ?? ?? ?? ?? ?? = = ( e q 17) w here: gcd stands for g reatest common d ivisor f n = maximum integer boundary frequency < f vco1 f pd = frequency of the phase d etector and f vcok are the channel step frequencies where 0 < k < 2 24 -1, a s shown in figure 44 . figure 44. exact frequency tuning s ome fractional plls are able to achieve this by adjusting (shortening) the length of the phase a ccumulator (the denominator or the modulus of the d elta- s igma modulator) so that the d elta- s igma modulator phase accumulator repeats at an exact period related to the interval frequency ( f vcok - f vco(k-1) ) in figure 44 . consequently, the shortened accumulator results in more frequent repeating patterns and as a result often leads to spurious emissions at multiples of the repeating pattern period, or at harmonic frequencies of f vcok - f vco(k-1) . for example, in some applications, these intervals might represent the spacing between radio channels, and the spurious would occur at multiples of the channel spacing. t he h ittite method on the other hand is able to generate exact frequencies between adjacent integer- n boundaries while still using the full 24 bit phase accumulator modulus, thus achieving exact frequency steps with a high phase detector comparison rate, which allows h ittite plls to maintain excellent phase noise and spurious performance in the e xact frequency mode. 1.12.2.3.3 using h ittite e xact frequency mode i f the constraint in ( e q 17) is satisfed, h mc834lp6 ge is able to generate signals with zero frequency error at the desired vco frequency. e xact frequency mode may be re-confgured for each target frequency, or be set-up for a fxed f gcd which applies to all channels. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 36 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.2.4.4 c onfguring e xact frequency mode for a particular frequency 1. calculate and program the integer register setting r eg 03h = n int = foor( f vco /f pd ), where the foor function is the rounding down to the nearest integer. t hen the integer boundary frequency f n = n int ? f pd 2. calculate and program the exact frequency register value r eg 0ch = f pd /f gcd , where f gcd = gcd( f vco , f pd ) 3. calculate and program the fractional register setting r eg 04h ( ) 24 2 ceil n vco frac pd ff n f ?? ?? ?? ?? ?? ? = = , where ceil is the ceiling function meaning round up to the nearest integer. example: to confgure the HMC834LP6GE for exact frequency mode at f vco = 2800.2 mhz where phase detector (pd) rate f pd = 61.44 mhz proceed as follows: check ( e q 17) to confrm that the exact frequency mode for this f vco is possible. ( ) gcd gcd 14 6 66 3 gcd 14 gcd( , ) 2 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 pd pd vco f f f f and f f ?? ?? ?? ?? = = => = s ince ( e q 17) is satisfed, the h mc834lp6 ge can be confgured for exact frequency mode at f vco = 2800.2 m h z as follows: 1. n int = r eg 03h = 6 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. r eg 0ch = ( ) ( ) 66 66 61.44 10 61.44 10 512 200 120000 gcd , gcd 2800.2 10 ,61.44 10 pd pd vco f dh ff = = = = 3. t o program r eg 04h , the closest integer- n boundary frequency f n that is less than the desired vco frequency f vco must be calculated. f n = f pd ? n int . using the current example: ( ) ( ) 6 24 6 6 24 6 45 61.44 10 2764.8 . 2 2800.2 10 2764.8 10 2 then reg04h 9666560 938000 61.44 10 int n pd n vco pd n f f mhz ff ceil ceil d h f ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? = = = ? ? = = = = 1.12.2.5.5 h ittite e xact frequency c hannel mode i f it is desirable to have multiple, equally spaced, exact frequency channels that fall within the same interval (ie. f n f vcok < f n+1 ) where f vcok is shown in figure 44 and 1 k 2 14 , it is possible to maintain the same integer- n ( r eg 03h ) and exact frequency register ( r eg 0ch ) settings and only update the fractional register ( r eg 04h ) setting. t he e xact frequency channel mode is possible if ( e q 17) is satisfed for at least two equally spaced adjacent frequency channels, i.e. the channel step size. t o confgure the h mc834lp6 ge for e xact frequency channel mode, initially and only at the beginning, integer ( r eg 03h ) and exact frequency ( r eg 0ch ) registers need to be programmed for the smallest f vco frequency ( f vco1 in figure 44 ), as follows: 1. calculate and program the integer register setting r eg 03h = n int = foor( f vco1 /f pd ), where f vco1 is shown in figure 44 and corresponds to minimum channel vco frequency. t hen the lower integer boundary frequency is given by f n = n int ? f pd . 2. calculate and program the exact frequency register value r eg 0ch = f pd /f gcd, where f gcd = gcd(( f vcok+1 - f vcok ), f pd ) = greatest common divisor of the desired equidistant channel spacing and the p d frequency (( f vcok+1 - f vcok ) and f pd ). for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 37 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t hen, to switch between various equally spaced intervals (channels) only the fractional register ( r eg 04h ) needs to be programmed to the desired vco channel frequency f vcok in the following manner: r eg 04h = ( ) 24 2 ceil n vcok frac pd ff n f ?? ?? ?? ?? ?? ? = where f n = foor( f vco1 /f pd ), and f vco1 , as shown in figure 44 , represents the smallest channel vco frequency that is greater than f n . example: to confgure the HMC834LP6GE for exact frequency mode for equally spaced intervals of 100 khz where frst channel (channel 1) = f vco1 = 2800.200 mhz and phase detector (pd) rate f pd = 61.44 mhz proceed as follows: first check that the exact frequency mode for this f vco1 = 2800.2 m h z (channel 1) and f vco2 = 2800.2 m h z + 100 k h z = 2800.3 m h z (channel 2) is possible. ( ) ( ) gcd1 gcd1 gcd 2 gcd 2 12 14 14 6 66 3 gcd1 14 6 6 63 gcd 2 14 gcd( , ) gcd( , ) 22 61.44 10 gcd 2800.2 10 ,61.44 10 120 10 3750 2 61.44 10 gcd 2800.3 10 ,61.44 10 20 10 3750 2 pd pd pd pd vco vco ff f f f and f and f f f and f f f ?? ?? ?? ?? ?? ?? ?? ?? = = = => = = => = i f ( e q 17) is satisfed for at least two of the equally spaced interval (channel) frequencies f vco1 ,f vco2 ,f vco3 ,... f vcon , as it is above, h ittite e xact frequency channel mode is possible for all desired channel frequencies, and can be confgured as follows: 1. r eg 03h = 6 1 6 2800.2 10 45 2 61.44 10 vco pd f floor floor d dh f ?? ?? ?? ?? ?? ?? ?? ?? = = = 2. r eg 0ch = ( ) ( ) ( ) 66 36 1 61.44 10 61.44 10 3072 00 20000 gcd 100 10 ,61.44 10 gcd , pd pd vcok vcok f dc h f ff + = = = = ? where ( f vcok+1 - f vcok ) is the desired channel spacing (100 k h z in this example). 3. t o program r eg 04h the closest integer- n boundary frequency f n that is less than the smallest channel vco frequency f vco1 must be calculated. f n = foor( f vco1 /f pd ). using the current example: 6 6 6 2800.2 10 45 61.44 10 2764.8 61.44 10 n pd f f floor mhz ?? ?? ?? ?? = = = t hen r eg 04h ( ) ( ) 24 1 1 24 6 6 6 2 for channel 1 where 2800.2 2 2800.2 10 2764.8 10 9666560 938000 61.44 10 n vco vco pd ff ceil f mhz f ceil d h ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ? = = ? = = = 4. t o change from channel 1 ( f vco1 = 2800.2 m h z) to channel 2 ( f vco2 = 2800.3 m h z), only r eg 04h needs to be programmed, as long as all of the desired exact frequencies f vcok ( figure 44 ) fall between the same integer- n boundaries ( f n < f vcok < f n+1 ). i n that case r eg 04h = ( ) 24 6 6 6 2 2800.3 10 2764.8 10 9693867 93 61.44 10 ceil d eaabh ?? ?? ?? ?? ?? ?? ? = = , and so on. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 38 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.12.2.6 seed r egister & a utoseed mode t he start phase of the fractional modulator digital phase accumulator ( d p a ) may be set to one of four possible default values via the seed register r eg 06h [1:0] . i f a uto s eed r eg 06h [8] is set, then the h mc834lp6 ge will automatically reload the start phase into the d p a every time a new fractional frequency is selected. i f a uto s eed is not set, then the h mc834lp6 ge will start new fractional frequencies with the last value left in the d p a from the last frequency. h ence the start phase will effectively be random. certain zero or binary seed values may cause spurious energy correlation at specifc frequencies. correlated spurs are advantageous only in very special cases where the spurious are known to be far out of band and are removed in the loop flter. for most cases a random, or non zero, non-binary start seed is recommended. further, since the a uto s eed always starts the accumulators at the same place, performance is repeatable if a uto s eed is used. r eg 06h [1:0]=2 is recommended. 1.13 soft r eset & power- o n r eset t he h mc834lp6 ge features a hardware power on r eset (po r ). a ll chip registers will be reset to default states approximately 250 s after power up. t he pll subsystem s p i registers may also be soft reset by an s p i write to register rst_swrst ( r eg 00h ) . n ote that the soft reset does not clear the s p i mode of operation referred to in section 1.17. 2 . i t should be noted that the vco subsystem is not affected by the pll soft reset, the vco subsystem registers can only be reset by removing the power supply. note: if external power supplies or regulators have rise times slower than 250 s, then it is advised to write to the spi reset register ( r eg 00h [5]=1) immediately after power up, before any other spi activity. this will ensure starting from a known state. 1.14 power d own mode n ote that the vco subsystem is not affected by the c en or soft reset. h ence device power down is a two step process. first power down the vco by writing 0 to vco register 1 via r eg 05h and then power down the pll by pulling c en pin 17 low (assuming no s p i overrides ( r eg 01h [0]=1)). t his will result in all analog functions and internal clocks disabled. current consumption will typically drop below 10 a in power d own state. t he serial port will still respond to normal communication in power d own mode. i t is possible to ignore the c en pin, by clearing rst_chipen_pin_select ( r eg 01h [0]=0) . control of power d own mode then comes from the serial port register rst_chipen_from_spi, r eg 01h [1] . i t is also possible to leave various blocks on when in power d own (see r eg 01h ) , including: a. i nternal bias r eference s ources r eg 01h [2] b. p d block r eg 01h [3] c. cp block r eg 01h [4] d. r eference path buffer r eg 01h [5] e. vco path buffer r eg 01h [6] f. d igital i /o t est pads r eg 01h [7] t o turn off the vco r f buffer but leave the vco running and the pll locked write r eg 05h = 2 a 98(manual select) then write r eg 05h = 0 d 88(disable vco r f buffer) t o re-enable the r f buffer write r eg 05h =0f88( e nable vco r f buffer) 1.15 c hip i dentifcation pll subsystem version information may be read by reading the content of read only register, chip_ id in r eg 00h . i t is not possible to read the vco subsystem version. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 39 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.16 g eneral purpose o utput ( g p o ) pin t he pll shares the l d _ sd o (lock- d etect/ s erial d ata out) pin to perform various functions. w hile the pin is most commonly used to read back registers from chip via the s p i , it is also capable of exporting a variety of interesting signals and real time test waveforms (including lock d etect). i t is driven by a tri-state cmo s driver with ~200 r out. i t has logic associated with it to dynamically select whether the driver is enabled, and to decide which data to export from the chip. i n its default confguration, after power-on-reset, the output driver is disabled, and only drives during appropriately addressed s p i reads. t his allows it to share the output with other devices on the same bus. d epending on the s p i mode, the read section of s p i cycle is recognized differently h mc s p i mode: t he driver is enabled during the last 24 bits of s p i read cycle (not during write cycles). open s p i mode: t he driver is enabled if the chip is addressed - ie. t he last 3 bits of s p i cycle = 000b before the rising edge of sen ( n ote a ). t o monitor any of the g po signals, including lock d etect, set r eg 0fh [7] = 1 to keep the sd o driver always on. t his stops the l d o driver from tri-stating and means that the sd o line cannot be shared with other devices. t he chip will naturally switch away from the g po data and export the sd o during an s p i read ( n ote b). t o prevent this automatic data selection, and always select the g po signal, set prevent a utomux of sd o ( r eg 0fh [6] = 1). t he phase noise performance at this output is poor and uncharacterized. a lso, the g po output should not be toggling during normal operation. otherwise the spectral performance may degrade. n ote that there are additional controls available, which may be helpful if sharing the bus with other devices: ? t o allow the driver to be active (subject to the conditions above) even when the chip is disabled - set r eg 01h [7] = 0. ? t o disable the driver completely, set r eg 08h [5] = 0 (it takes precedence over all else). ? t o disable either the pull-up or pull-down sections of the driver, r eg 0fh [8] = 1 or r eg 0fh [9] = 1 respectively. note a: if sen rises before sck has clocked in an invalid (non-zero) chip -address, the HMC834LP6GE will start to drive the bus. note b: in open mode, the active portion of the read is defned between the 1 st sck rising edge after sen, to the next rising edge of sen. e xample s cenarios: ? d rive sd o during reads, tri-state otherwise (to allow bus-sharing) ? n o action required. ? d rive sd o during reads, lock d etect otherwise ? s et g po s elect r eg 0fh [4:0] = 00001 (which is default) ? s et prevent g po driver disable ( r eg 0fh [7] = 1) ? a lways drive lock d etect ? s et prevent a utomux of sd o r eg 0fh [6] = 1 ? s et g po s elect r eg 0fh [4:0]= 00001 (which is default) ? s et prevent g po driver disable ( r eg 0fh [7] = 1)) t he signals available on the g po are selected by changing g po s elect, r eg 0fh [4:0]. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 40 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17 serial port 1.17.1 serial port modes of o peration t he h mc834lp6 ge serial port interface can operate in two different modes of operation. a. h mc s p i h mc mode ( h mc legacy mode) - s ingle slave per h mc s p i bus b. h mc s p i open mode - up to 8 slaves per h mc s p i bus. both modes support 5-bits of register address space. h mc mode can support up to 6 bits of register address. r egister 0 has a dedicated function in each mode. open mode allows wider compatibility with other manufacturers sp i protocols. t able 4. r egister 0 c omparison - single vs multi-user modes single user hmc mode multi-user open mode read chip id 24-bits chip id 24-bits write s oft r eset, g eneral s trobes r ead a ddress [4:0] s oft reset [5] g eneral s trobes [23:6] 1.17. 2 h m c sp i protocol d ecision after power- o n r eset on power up both types of modes are active and listening. a decision to select the desired s p i protocol is made on the frst occurrence of sen or s clk following a hard reset, after which the protocol is fxed and only changeable by cycling the power off and o n . a. i f a rising edge on sen is detected frst h mc mode is selected. b. i f a rising edge on s clk is detected frst open mode is selected. 1.17.3 serial port h m c mode - single p ll h mc mode (legacy mode) serial port operation can only address and talk to a single pll, and is compatible with most h ittite plls and plls with i ntegrated vcos. t he h mc mode protocol, shown in fgures figure 45 and figure 46 , is designed for a 4 wire interface with a fxed protocol featuring a. 1 r ead/ w rite bit b. 6 a ddress bits c. 24 data bits d. 3 wire for w rite only, 4 wire for r ead/ w rite capability 1.17.3.1 h m c mode - serial port write o peration a v dd = d v dd = 3v 10%, agnd = dgnd = 0v t able 5. sp i h m c mode - w rite t iming c haracteristics parameter conditions min. typ. max units t 1 sen to s clk setup time 8 ns t 2 sdi to s clk setup time 3 ns t 3 s clk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 s ck to sen fall 10 ns max s erial port clock s peed 50 m hz for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 41 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a typical h mc mode write cycle is shown in figure 45 . a. t he master (host) both asserts sen ( s erial port e nable) and clears sdi to indicate a write cycle, followed by a rising edge of s ck. b. t he slave (synthesizer) reads sdi on the 1st rising edge of s ck after sen . sdi low indi cates a w rite cycle (/ wr ). c. h ost places the six address bits on the next six falling edges of s ck, m s b frst. d. s lave shifts the address bits in the next six rising edges of s ck (2-7). e. h ost places the 24 data bits on the next 24 falling edges of s ck, m s b frst. f. s lave shifts the data bits on the next 24 rising edges of s ck (8-31). g. t he data is registered into the chip on the 32nd rising edge of s ck. h. sen is cleared after a minimum delay of t 5 . t his completes the write cycle. figure 45. hmc mode - serial port timing diagram - write 1.17.3 . 2 h m c mode - serial port read o peration a typical h mc mode read cycle is shown in figure 46 . a. t he master (host) asserts both sen ( s erial port e nable) and sdi to indicate a read cycle, followed by a rising edge s clk. n ote: t he lock d etect (l d ) function is usually multiplexed onto the l d _ sd o pin. i t is suggested that l d only be considered valid when sen is low. i n fact l d will not toggle until the frst active data bit toggles on l d _ sd o, and will be restored immediately after the trailing edge of the l s b of serial data out as shown in figure 46 . b. t he slave ( h mc834lp6 ge ) reads sdi on the 1st rising edge of s clk after sen . sdi high initiates the read cycle ( rd ) c. h ost places the six address bits on the next six falling edges of s clk, m s b frst. d. s lave registers the address bits on the next six rising edges of s clk (2-7). e. s lave switches from lock d etect and places the requested 24 data bits on sd _l d o on the next 24 rising edges of s ck (8-31), m s b frst . f. h ost registers the data bits on the next 24 falling edges of s ck (8-31). g. s lave restores lock d etect on the 32nd rising edge of s ck. h. d e-assertion of sen completes the cycle for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 42 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z t able 6. sp i h m c mode - r ead t iming c haracteristics parameter conditions min. typ. max units t 1 sen to s clk setup time 8 ns t 2 sdi to s clk setup time 3 ns t 3 s clk to sdi hold time 3 ns t 4 sen low duration 20 ns t 5 s clk to sd o delay 8.2ns+0.2 ns/pf ns t 6 r ecovery t ime 10 ns figure 46. hmc mode - serial port timing diagram - read 1.17.4 serial port o pen mode t he s erial port open mode, shown in figure 47 and figure 48 , features: a. compatibility with general serial port protocols that use shift and strobe approach to communication b. compatible with h ittite pll with i ntegrated vco solutions, useful to address multiple chips of various types from a single serial port bus. t he open mode protocol has the following general features: a. 3-bit chip address , can address up to 8 devices connected to the serial bus b. w ide compatibility with multiple protocols from multiple vendors c. s imultaneous w rite/ r ead during the s p i cycle d. 5-bit address space e. 3 wire for w rite only capability, 4 wire for r ead/ w rite capability h ittite plls with integrated vcos support open mode. s ome legacy pll and microwave plls with integrated vcos only support h mc mode. consult the relevant data sheets for details. t ypical serial port operation can be run with s clk at speeds up to 50 m h z. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 43 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17.4.1 o pen mode - serial port write o peration a v dd = d v dd = 3v 10%, agnd = dgnd = 0v t able 7. sp i o pen mode - write t iming c haracteristics parameter conditions min. typ. max units t 1 sdi setup time to s clk r ising e dge 3 ns t 2 s clk r ising e dge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 s clk 32 r ising e dge to sen r ising e dge 10 ns t 6 r ecovery t ime 20 ns max s erial port clock s peed 50 m hz a typical write cycle is shown in figure 47 . a. t he master (host) places 24-bit data, d23:d0, m s b frst, on sdi on the frst 24 falling edges of s clk. b. the slave ( h mc834lp6 ge ) shifts in data on sdi on the frst 24 rising edges of s clk c. master places 5-bit register address to be written to, r4:r0, m s b frst, on the next 5 falling edges of s clk (25-29) d. s lave shifts the register bits on the next 5 rising edges of s clk (25-29). e. master places 3-bit chip address, a2:a0, m s b frst, on the next 3 falling edges of s clk (30-32). h ittite reserves chip address a2:a0 = 000 for all r f pll with i ntegrated vcos. f. s lave shifts the chip address bits on the next 3 rising edges of s clk (30-32). g. master asserts sen after the 32nd rising edge of s clk. h. s lave registers the sdi data on the rising edge of sen . figure 47. open mode - serial port timing diagram - write 1.17.4 . 2 o pen mode - serial port read o peration a typical read cycle is shown in figure 48 . i n general, in open mode the l d _ sd o line is always active during the write cycle. d uring any open mode s p i cycle l d _ sd o will contain the data from the current address written in r eg0h[7:3]. i f r eg0h[7:3] is not changed then the same data will always be present on l d _ sd o when an open mode cycle is in progress. i f it is desired to read from a specifc address, it is necessary in the frst s p i cycle to write the desired address to r eg0h[7:3], then in the next s p i cycle the desired data will be available on l d _ sd o. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 44 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z a n example of the open mode two cycle procedure to read from any random address is as follows: a. t he master (host), on the frst 24 falling edges of s clk places 24-bit data, d23:d0, m s b frst, on sdi as shown in figure 48 . d23:d5 should be set to zero. d4:d0 = address of the register to be read on the next cycle. b. the slave ( h mc834lp6 ge ) shifts in data on sdi on the frst 24 rising edges of s clk c. master places 5-bit register address , r4:r0, (the read address register), m s b frst, on the next 5 falling edges of s clk (25-29). r4:r0=00000. d. s lave shifts the register bits on the next 5 rising edges of s clk (25-29). e. master places 3-bit chip address, a2:a0, m s b frst, on the next 3 falling edges of s clk (30-32)..chip address is always 000 for r f pll with i ntegrated vcos. f. s lave shifts the chip address bits on the next 3 rising edges of s clk (30-32). g. master asserts sen after the 32nd rising edge of s clk. h. s lave registers the sdi data on the rising edge of sen . i. master clears sen to complete the the address transfer of the two part read cycle. j. i f one does not wish to write data to the chip at the same time as we do the second cycle , then it is recommended to simply rewrite the same contents on sdi to r egister zero on the read back part of the cycle. k. master places the same sdi data as the previous cycle on the next 32 falling edges of s clk. l. s lave ( h mc834lp6 ge ) shifts the sdi data on the next 32 rising edges of s clk. m. s lave places the desired read data (ie. data from the address specifed in r eg 00h [7:3] of the frst cycle) on l d _ sd o which automatically switches to sd o mode from l d mode, disabling the l d output. m. master asserts sen after the 32nd rising edge of s ck to complete the cycle and revert back to lock d etect on l d _ sd o. t able 8. sp i o pen mode - r ead t iming c haracteristics parameter conditions min. typ. max units t 1 sdi setup time to s clk r ising e dge 3 ns t 2 s clk r ising e dge to sdi hold time 3 ns t 3 sen low duration 10 ns t 4 sen high duration 10 ns t 5 s clk r ising e dge to sd o time 8.2ns+0.2ns/pf ns t 6 r ecovery ti me 10 ns t 7 sck 32 rising e dge to sen rising edge 10 ns for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 45 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.17.4 .3 h m c sp i o pen mode read o peration - 2 c ycles figure 48. serial port timing diagram - read for more information on using the g po pin while in s p i open mode please see section 1.16. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 46 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.18 c onfguration at start-up t o confgure the pll after power up, follow the instructions below: 1. confgure the reference divider (write to r eg 02h ), if required. 2. confgure the delta-sigma modulator (write to r eg 06h ). ? confguration involves selecting the mode of the delta-sigma modulator (mode a or mode b), selection of the delta-sigma modulator seed value, and confguration of the delta-sigma modulator clock scheme. i t is recommended to use the values found in the h ittite pll evaluation board control software register fles. 3. confgure the charge pump current and charge pump offset current (write to r eg 09h ) 4. confgure the vco s ubsystem (write to r eg 05h , for more information see section 1.19 , and 3.0 vco s ubsystem r egister map . d etailed writes to the vco subsystem via pll r eg 05h at start-up are available in the r egister s etting files found in the hi ttite pll e valuation s oftware received with a product evaluation kit or downloaded from www.hittite.com . 5. program the frequency of operation ? program the integer part (write to r eg 03h ) ? program the fractional part (write to r eg 04h ) 6. confgure the vco output divider/doubler, if needed in the vco subsystem via pll r eg 05h . once the h mc834lp6 ge is confgured after startup, in most cases the user only needs to change frequencies by writing to r eg 03h integer register, r eg 04h fractional register, and r eg 05h to change the vco output divider or doubler setting if needed, and possibly adjust the charge pump settings by writing to r eg 09h . for detailed and most up-to-date start-up confguration please refer to the appropriate r egister s etting files found in the hi ttite pll e valuation s oftware received with a product evaluation kit or downloaded from www.hittite.com . 1.19 v co serial port i nterface (sp i ) t he h mc834lp6 ge communicates with the internal vco subsystem via an internal 16 bit vco s erial port, (e.g. see figure 29 ). t he internal serial port is used to control the step tuned vco and other vco subsystem functions, such as r f output divider / doubler control and r f buffer enable. n ote that the internal vco subsystem s p i (v s p i ) runs at the rate of the a utocal f s m clock, t fsm , (section 1. 2.1 ) where the f s m clock frequency cannot be greater than 50 m h z. t he v s p i clock rate is set by r eg 0 ah [14:13]. w rites to the vcos control registers are handled indirectly, via writes to r eg 05h of the pll. a write to pll r eg 05h causes the pll subsystem to forward the packet, m s b frst, across its internal serial link to the vco subsystem, where it is interpreted. t he vco serial port has the capability to communicate with multiple subsystems inside the i c. for this reason each subsystem has a subsystem id , r eg 05h [2:0]. e ach subsystem has multiple registers to control the functions internal to the subsystem, which may be different from one subsystem to the next. h ence each subsystem has internal register addresses bits ( r eg 05h [6:3]) finally the data required to confgure each register within the vco subsystem is contained in r eg 05h [15:7]. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 47 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 1.19.1 vsp i use of r eg05h t he packet data written into, r eg 05h is sub-parsed by logic at the vco subsystem into the following 3 felds: 1. [2:0] - 3 bits - vco_ id , target subsystem address = 000b. 2. [6:3] - 4 bits - vco_ regaddr , the internal register address inside the vco subsystem. 3. [15:7] - 9- bits- vco_ data , data feld to write into the vco register. for example, to write 0_1111_1110 into register 2 of the vco subsystem (vco_ id = 000b), and set the vco output divider to divide by 62, the following needs to be written to r eg 05h =0 _1111_1110, 0 010, 0 0 0 b. d uring a utocal, the a utocal controller only updates the data feld of r eg 05h . t he vco subsystem register address ( r eg 05h [6:3]) must be set to 0000 for the a utocal data to be sent to the correct address. vco subsystem id and register address are not modifed by the a utocal state machine. h ence, if a manual access is done to a vco s ubsystem register the user must reset the register address to zero before a change of frequency which will re-run a utocal. s ince every write to r eg 05h will result in a transfer of data to the vco subsystem, if the vco subsystem needs to be reset manually, it is important to make sure that the vco switch settings are not changed. h ence the switch settings in r eg 10h [7:0] need to be read frst, and then rewritten to r eg 05h [15:8]. i n summary, frst read r eg 10h , then write to r eg 05h as follows: r eg 10h[7:0] = vv x yyyyy r eg 05h = vv x yyyyy 0 0000 iii r eg 05h [2:0] = iii, subsystem id , 3 bits (000) r eg 05h [6:3] = 0000, subsystem register address r eg 05h [7] = 0 , calibration tune voltage off r eg 05h [12:8] = yyyyy, vco caps r eg 05h [13] = x, dont care r eg 05h [15:14] = vv, vco s elect for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 48 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.0 p ll r egister map 2.1 r eg 00h id r egister ( r ead o nly) bit type name width default description [23:0] ro chip_ id 24 a 7975 h mc834lp6 ge chip id 2.2 r eg 00h o pen mode r ead a ddress/ r s t strobe r egister ( w rite o nly) bit type name width default description [4:0] wo r ead a ddress 5 - ( write o n ly) r ead a ddress for next cycle - open mode only [5] wo s oft r eset 1 - s oft r eset - both s p i modes reset (set to 0 for proper operation) [23:6] wo n ot d efned 18 - n ot d efned (set to 0 for proper operation) 2.3 r eg 01h rs t r egister ( d efault 000002h) bit type name width default description [0] r/ w rst_chipen_pin_select 1 0 1 = take pll enable via c en pin, see power d own mode description 0 = take pll enable via s p i (rst_chipen_from_spi) r eg01[1] [1] r/ w rst_chipen_from_spi 1 1 s p i s pll enable bit [2] r/ w keep_bias_on 1 0 when pll is disabled, keeps internal bias generators on, ignores chip enable control. [3] r/ w keep_p d _on 1 0 when pll is disabled, keeps p d circuit on, ignores chip enable control [4] r/ w ke e p_ cp_ o n 1 0 when pll is disabled, keeps charge pump on, ignores chip enable control [5] r/ w keep_ r ef_buf_on 1 0 when pll is disabled, keeps r eference buffer block on, ignores chip enable control [6] r/ w keep_vco_on 1 0 when pll is disabled, keeps vco divider buffer on, ignores chip enable control [7] r/ w keep_ g po_driver_on 1 0 when pll is disabled, keeps g po output d river on, ignores chip enable control [8] r/ w r eserved 1 0 r eserved [9] r/ w r eserved 1 0 r eserved 2.4 r eg 02h re f di v r egister ( d efault 000001h) bit type name width default description [13:0] r/ w rdiv 14 1 r eference d ivider r value (e q 13)) d ivider use also requires refbuf e n r eg08[3]=1and d ivider min 1d max 16383d for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 49 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.5 r eg 03h frequency r egister - i nteger part ( d efault 000019h) bit type name width default description [18:0] r/ w intg 19 25d vco d ivider i nteger part, used in all modes, see ( e q 13) fractional mode min 20d max 2 19 -4 = 7fffch = 524,284d i nteger mode min 16d max 2 19 -1 = 7ffffh = 524,287d 2.6 r eg 04h frequency r egister - fractional part ( d efault 000000h) bit type name width default description [23:0] r/ w frac 24 0 vco d ivider fractional part (24-bit unsigned) see fractional frequency t uning used in fractional mode only ( n frac = r eg 04h /2 24 min 0d max 2 24 -1 2.7 r eg 05h v co sp i r egister ( d efault 000000h) bit type name width default description [2:0] r/ w vco s ubsystem_ id , 3 0 i nternal vco s ubsystem id [6:3] r/ w vco s ubsystem register address 4 0 for interfacing with the vco please see section 1.19 . [15:7] r/ w vco s ubsystem data 9 0 n ote: r eg05h is a special register used for indirect addressing of the vco subsystem. w rites to r eg05h are automatically forwarded to the vco subsystem by the vco s p i state machine controller. r eg05h is a r ead- w rite register. h owever, r eg05h only holds the contents of the last transfer to the vco subsystem. h ence it is not possible to read the full contents of the vco subsystem. only the content of the last transfer to the vco subsystem can be read. please take note special considerations for a utocal related to r eg05h for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 50 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.8 r eg 06h s d c f g r egister ( d efault 200b4 a h) bit type name width default description [1:0] r/ w seed 2 2 s elects the s eed in fractional mode 00: 0 seed 01: lsb seed 02: b29 d 08h seed 03: 50f1c d h seed n ote; w rites to this register are stored in the h mc834lp6 ge and are only loaded into the modulator when a frequency change is executed and if a uto s eed reg06h[8] =1 [3:2] r/ w order 2 2 s elect the modulator t ype 0: 1st order 1: 2nd order 2: t ype 1 mode b 3: t ype 2 mode a [6:4] r/ w r eserved 3 4 program to 7d [7] r/ w frac_bypass 1 0 0: use modulator, r equired for fractional mode, 1: bypass modulator, r equired for i nteger mode n ote: i n bypass fractional modulator output is ignored, but fractional modulator continues to be clocked if frac_ rstb =1, can be used to test the isolation of the digital fractional modulator from the vco output in integer mode [8] r/ w a uto s eed 1 1 1: loads the seed whenever the frac register is written 0: when frac register write changes frequency, modulator starts with previous contents [9] r/ w clkrq_refdiv_sel 1 1 selects the modulator clock source- for t est only 1: vco divider clock ( r ecommended for normal operation) 0: r ef divider clock i gnored if bits [10] or [21] are set [10] r/ w sd modulator clk s elect 1 0 0 - sd auxclk, 1- sd vco clock delay ( r ecommended) [11] r/ w sd e nable 1 1 0: disable frac core, use for i nteger mode or i nteger mode with c sp 1: e nable frac core, required for fractional mode, or i nteger isolation testing t his register controls whether a utocal starts on an i nteger or a fractional write [12] r/ w r eserved 1 0 [13] r/ w r eserved 1 0 [15:14] r/ w r eserved 2 0 [17:16] r/ w r eserved 2 0 program to 3d [18] r/ w b ist e nable 1 0 e nable built in s elf t est [20:19] r/ w rd iv b ist cycles 2 0 rd iv b ist cycles 00: 1032 01: 2047 10: 3071 11: 4095 [21] r/ w auto_clock_confg 1 1 s et to 0 for f pd > 50 m h z [22] r/ w r eserved 1 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 51 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.9 r eg 07h l ock d etect r egister ( d efault 00014 d h) bit type name width default description [2:0] r/ w lkd_wincnt_max 3 5d lock detect window sets the number of consecutive counts of divided vco that must land inside the lock d etect w indow to declare lock 0: 5 1: 32 2: 96 3: 256 4: 512 5: 2048 6: 8192 7: 65535 [3] r/ w e nable i nternal lock d etect 1 1 see section 1.16 [5:4] r/ w r eserved 2 0 r eserved [6] r/ w lock d etect w indow type 1 1 lock d etection w indow t imer s election 1: d igital programmable timer 0: a nalog one shot, nominal 10 ns window [9:7] r/ w l d d igital w indow duration 3 2 0 lock d etection - d igital w indow d uration 0: 1/2 cycle 1: 1 cycle 2: 2 cycles 3: 4 cycles 4: 8 cycles 5: 16 cycles 6: 32 cycles 7: 64 cycles [11:10] r/ w l d d igital t imer freq control 2 0 lock d etect d igital t imer frequency control 00 fastest 11 slowest [12] r/ w l d t imer t est mode 1 0 1: force t imer clock o n continuously - for t est only 0: n ormal t imer operation - one shot [13] r/ w a uto r elock - one t ry 1 0 1: a ttempts to relock if lock d etect fails for any reason only tries once. for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 52 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.10 r eg 08h a nalog en r egister (d efault c1b e ffh) bit t ype n ame w idth d efault d escription [0] r/ w bias_en 1 1 e nables main chip bias reference [1] r/ w cp_en 1 1 charge pump enable [2] r/ w pd _en 1 1 p d enable [3] r/ w refbuf_en 1 r eference path buffer enable [4] r/ w vcobuf_en 1 1 vco path r f buffer enable [5] r/ w gpo_pad_en 1 1 0 - pin l d _ sd o disabled 1 - and r egfh[7]=1 , pin l d _ sd o is always on required for use of g po port 1 - and r egfh[7]=0 s p i l d o_ s p i is off if unmatched chip address is seen on the s p i , allowing a shared s p i with other compatible parts [6] r/ w reserved 1 1 reserved [7] r/ w vco_ d iv_clk_to_dig_en 1 1 vco d ivider clock to d igital e nable [8] r/ w reserved 1 0 reserved [9] r/ w prescaler clock enable 1 1 prescaler clock enable [10] r/ w vco buffer and prescaler bias e nable 1 1 vco buffer and prescaler bias e nable [11] r/ w charge pump i nternal opamp enable 1 1 s hould be programmed to 1 [14:12] r/ w reserved 3 011 reserved [17:15] r/ w reserved 3 011 reserved [18] r/ w spare 1 0 spare [19] r/ w reserved 1 0 reserved [20] r/ w reserved 1 0 reserved program to 0 [21] r/ w h igh frequency r eference 1 0 program to 1 for x ta l > 200 m h z [22] r/ w reserved 1 1 reserved program to 1 [23] r/ w reserved 1 1 reserved program to 1 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 53 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2 .11 r eg 09h c harge pump r egister ( d efault 403264h) bit t ype n ame w idth d efault d escription [6:0] r/ w cp dn g ain 7 100d 64h charge pump dn g ain control 20 a step a ffects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54m a [13:7] r/ w cp up g ain 7 100d 64h charge pump up g ain control 20 a per step a ffects fractional phase noise and lock detect settings 0d = 0 a 1d = 20 a 2d = 40 a ... 127d = 2.54m a [20:14] r/ w offset magnitude 7 0 charge pump offset control 5 a /step a ffects fractional phase noise and lock detect settings 0d = 0 a 1d = 5 a 2d = 10 a ... 127d = 635 a [21] r/ w offset up enable 1 0 recommended setting = 0 [22] r/ w offset dn enable 1 1 recommended setting = 1 in fractional mode, 0 otherwise [23] r/ w h ikcp 1 0 h ikcp h igh current charge pump for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 54 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.12 r eg 0 a h v co a uto c al c onfguration r egister ( d efault 002205h) bit t ype n ame w idth d efault d escription [2:0] r/ w vtune r esolution 3 5 r d ivider cycles 0 - 1 1 - 2 2 - 4 3 - 8 4 - 32 5 - 64 6 - 128 7 - 256 [5:3] r/ w vco curve a djustment 3 0 vco curve a djustment vs t emp for a utocal 0 - d isabled 1 : + 1 curve 2: +2 curves 3: +3 curves 4: -4 curves 5: -3 curves 6: -2 curves 7: -1 curve [7:6] r/ w w ait s tate s et up 2 0 w ait s tate s etup 100 t fs m see section 1.2.4 t mmt = 1 measurement cycle of a utocal 0: w ait only at s tartup 1: w ait on startup and after frst t mmt cycle 2: w ait on startup and after frst two t mmt cycles 3: w ait on startup and after frst three t mmt cycles [9:8] r/ w n um of sar b i ts in vco 2 0 n umber of sar bits in vco 0: 8 - recommended 1: 7 2: 6 3: 5 [10] r/ w force curve 1 0 force curve sent during t uning t une from r eg5 [11] r/ w bypass vco t uning 1 0 bypass vco t uning [12] r/ w n o v s p i t rigger 1 0 d ont trigger a transfer on writes to r eg 05h [14:13] r/ w fs m/v s p i clock s elect 2 1 s et the a utocal f s m and v s p i clock (50 m h z maximum) 0: i nput crystal r eference 1: i nput crystal r eference/4 2: i nput crystal r eference/16 3: i nput crystal r eference/32 [15] r/ w xtal falling e dge for f s m 1 0 use the falling e dge of the xtal for f s m a utocal clock - r equired for b ist [16] r/ w force rd ivider bypass 1 0 force the r d ivider bypass for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 55 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.13 r eg 0bh p d r egister ( d efault 7c061h) bit t ype n ame w idth d efault d escription [2:0] r/ w p d _del_sel 3 1 s ets p d reset path delay ( r ecommended setting 001) [3] r/ w s hort p d i nputs 1 0 s horts the inputs ot the phase frequency detector - t est only [4] r/ w pd_phase_sel 1 0 i nverts the p d polarity (program to 0) 0- use with a positive tuning slope vco and passive loop filter (default) 1- use with a n egative s lope vco or with an inverting a ctive loop filter with a positive s lope vco [5] r/ w p d _up_en 1 1 e nables the p d up output [6] r/ w p d _dn_en 1 1 e nables the p d dn output [8:7] r/ w cs p mode 2 0 cycle s lip prevention mode e xtra current is driven into the loop flter when the phase error is larger than: 0: d isabled 1: 5.4ns 2: 14.4ns 3: 24.1ns t his delay varies by +- 10% with temperature, and +- 12% with process. [9] r/ w force cp up 1 0 forces cp up output on - use for t est only [10] r/ w force cp dn 1 0 forces cp dn output on - use for t est only [11] r/ w force cp m i d r ail 1 0 force cp m i d r ail - use for t est only [14:12] r/ w r eserved 3 4 program to 100 [16:15] r/ w cp i nternal op a mp bias 2 3 program to 11 [18:17] r/ w mcounter clock g ating 2 3 mcounter clock g ating 0: mcounter off 1: n <128 2: n < 1023 3: a ll clocks o n ( r ecommended setting 11) [19] r/ w reserved 1 0 program to 0 [21:20] r/ w reserved 2 0 program to 00 [23:22] r/ w reserved 2 0 program to 00 2.14 r eg 0 c h e xact frequency mode r egister ( d efault 000000h) bit t ype n ame w idth d efault d escription [13:0] r/ w n umber of channels per fpd 14 0 comparison frequency divided by the correction r ate, must be an integer. frequencies at exactly the correction rate will have zero frequency error. 0: d isabled 1: d isabled 2:16383d (3fffh) for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 56 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.15 r eg 0fh g p o _sp i _ rdi v r egister ( d efault 000001h) bit t ype n ame w idth d efault d escription [4:0] r/ w gpo_select 5 1d s ignal selected here is output to sd o pin when enabled 0: d ata from r eg0f[5] 1: lock d etect output 2. lock d etect t rigger 3: lock d etect w indow output 4: r ing osc t est 5. pullup h ard from c s p 6. pull dn hard from c s p 7. r eserved 8: r eference buffer output 9: r ef d ivider output 10: vco divider output 11. modulator clock from vco divider 12. a uxiliary clock 13. a ux s p i clock 14. a ux s p i e nable 15. a ux s p i d ata out 16. p d dn 17. p d up 18. sd 3 clock d elay 19. sd 3 core clock 20. a uto s trobe i nteger w rite 21. a utostrobe frac w rite 22. a utostrobe a ux s p i 23. s p i latch e nable 24. vco d ivider s ync r eset 25. s eed load s trobe 26.-29 n ot used 30. s p i output buffer e n 31. s oft rst b [5] r/ w g po t est d ata 1 0 1 - g po t est d ata [6] r/ w prevent a utomux sd o 1 0 1- outputs g po data only 0 - a utomuxes between sd o and g po data [7] r/ w l d o d river a lways on 1 0 1- l d _ sd o pin d river always on 0 - l d _ sd o pin driver only on during s p i read cycle [8] r/ w d isable pf et 1 0 program to 0 [9] r/ w d isable n f et 1 0 program to 0 for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 57 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 2.16 r eg 10h v co t une r egister ( d efault 000020h) bit t ype n ame w idth d efault d escription [7:0] ro vco s witch s etting 8 32 r ead only r egister. i ndicates the vco switch setting selected by the a utocal state machine to yield the nearest free running vco frequency to the desired operating frequency. n ot valid when r eg10h[8] = 1, a utocal busy. n ote if a manual change is done to the vco switch settings this register will not indicate the current vco switch position. 0 = highest frequency 1 = 2nd highest ... 256 = lowest frequency n ote: vco subsystems may not use all the m s bs, in which case the unused bits are dont care [8] ro a utocal busy 1 0 busy when a utocal state machine is searching for the nearest switch setting to the requested frequency. 2.17 r eg 11h s ar r egister ( d efault 007fffh) bit t ype n ame w idth d efault d escription [18:0] ro sar e rror mag counts 19 2 19 -1 sar e rror magnitude counts [19] ro sar e rror s ign 1 0 sar e rror s ign 0=+ve 1=-ve 2.18 r eg 12h g p o 2 r egister ( d efault 000000h) bit t ype n ame w idth d efault d escription [0] ro g po 1 0 g po s tate [1] ro lock d etect 1 0 lock d etect s tatus 1 = locked 0 = unlocked 2.19 r eg 13h b i s t r egister ( d efault 000000h) bit t ype n ame w idth d efault d escription [15:0] ro b ist s ignature 19 4697d b ist s ignature [16] ro b ist busy 1 0 b ist busy for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 58 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.0 v co subsystem r egister map please note that the vco subsystem uses indirect addressing via r eg 05h . for more detailed information on how to write to the vco subsystem please see section 1.19 vco s erial port i nterface ( s p i ) . 3.1 v co_ r eg 00h t uning bit type name width default description [0] wo cal 1 0 vco tune voltage is redirected to a temperature compensated calibration voltage [8:1] wo ca p s 8 16 vco sub-band selection. 0 - max frequency 1111 1111 - min fre quen cy. n ot all sub-bands are used on the various products. 3.2 v co _ r eg 01h e nables bit type name width default description [0] wo master e nable vco s ubsystem 1 1 0 - a ll vco subsystem blocks off manual mode ( vco_ r eg 03h [2] = 1) 1- and ed with local enables only a uto mode ( vco_ r eg 03h [2] = 0) 1- master enable ignores local enables [1] wo manual mode pll buffer enable 1 1 e nables pll buffer in manual mode only [2] wo manual mode r f buffer enable 1 1 e nables r f buffer to output in manual mode only [3] wo manual mode d ivide by 1 enable 1 1 e nables r f divide by 1 in manual mode only [4] wo manual mode r f d ivider enable 1 1 e nables r f divider in manual mode only [8:5] wo dont care 4 0 dont care for example, to turn disable the r f buffer in the vco subsystem and mute the output of the h mc834lp6 ge , bit 2 in vco_ r eg01h needs to be cleared. i f the other bits are left unchanged, then 0 0001 1011 needs to be written into vco r eg01h. t he vco subsystem register is accessed via a write to pll subsystem r eg 05h = 0 0001 1011 0001 000 = d 88h r eg 05h [2:0] = 000; vco subsystem id 0 r eg 05h [6:3] = 0001; vco subsystem register address r eg 05h [7] = 1; master enable r eg 05h [8] = 1; pll buffer enable r eg 05h [9] = 0; d isable r f buffer r eg 05h [10] = 1; d ivide by 1 enable r eg 05h [11] = 1; r f d ivider enable r eg 05h [16:12] = 0; dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 59 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.3 v co_ r eg 02h biases bit type name width default description [5:0] wo r f d ivide ratio 6 1 0 - mute, vco and pll buffer on, r f output stages off 1 - fo 2 - fo/2 3 - invalid, defaults to 2 4 - fo/4 5 - invalid, defaults to 4 6 - fo/6 ... 60 - fo/60 61 - invalid, defaults to 60 62 - fo/62 > 62 - invalid, defaults to 62 n ote: t his register automatically controls the enables to the, r f output buffer, r f divider, r f divide by 1 path, and requires master e nable ( vco_ r eg 01h [0] = 1) and a uto r fo mode ( vco_ r eg 03h [2] = 0) n ote: bit[0] is a dont care in manual r fo mode. [7:6] wo r f output buffer gain control 2 3 11 - max g ain 10 - max g ain - 3 db 01 - max g ain - 6 db 00 - max g ain - 9 db [8] wo d ivider output stage gain control 1 0 1 - max g ain 0 - max g ain - 3 db used to fatten the output power level across frequency ? for divide-by 1 or divide-by 2 it is recommended to set this bit to 1. 0 will reduce output power and degrade noise foor performance. ? for divide-by 4 or higher, it is recommended to set this bit to 0 to maintain fat output power across divider settings. s etting this bit to 1, with divide-by 4 or higher provides higher output power compared to the divide- by 1 or two case. for example, to write 0_1111_1110 into vco_ r eg02h vco subsystem (vco_ id = 000b), and set the vco output divider to divide by 62, the following needs to be written to r eg 05h =0 _1111_1110, 0 010, 0 0 0 b. r eg 05h [2:0] = 00; subsystem id 0 r eg 05h [6:3] = 0010; vco register address 2d r eg 05h [16:7] = 0 _1111_1110 ; d ivide by 62, max output r f gain, d ivider output stage gain = 0 3.4 v co_ r eg 03h c onfg bit type name width default description [0] wo fundamental/ d oubler mode s election 1 1 0- e nable the frequency doubler mode of operation 1- e nable fundamental mode of operation - for more information please see vco s ubsystem section. [1] wo reserved 1 0 reserved [2] wo manual r fo mode 1 0 0 - a uto r fo mode (recommended) 1 - manual r fo mode a uto r fo mode controls output buffers and r f divider enables according to r f divider setting in vco_ r eg 02h [5:0] manual r fo mode requires manual enables of individual blocks via vco_ r eg01h [4:3] wo r f buffer bias 2 2 program to 10 when fundamental mode enabled program to 00 when doubler mode enabled [8:5] wo s pare 4 2 dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 60 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z 3.5 v co _ r eg 04h c al/bias s pecifed performance is only guaranteed with the required settings in this table. other settings are not supported. bit type name width default description [2:0] wo vco bias 3 1 program to 5d [4:3] wo pll buffer bias 2 1 program to 1d [6:5] wo fndlmtr bias 2 2 program to 3d [8:7] wo preset cal 0 2 1 program to 2d 3.6 v co_ r eg05h c f_ c al bit type name width default description [1:0] wo cf l 2 2 program to 0d [3:2] wo cf ml 2 2 program to 3d [5:4] wo cf m h 2 2 program to 3d [7:6] wo cf h 2 2 program to 3d [8] wo s pare 1 0 program to 0d 3.7 v co_ r eg06h msb c al bit type name width default description [1:0] wo m s b l 2 3 program to 3d [3:2] wo m s b ml 2 3 program to 3d [5:4] wo m s b m h 2 3 program to 3d [7:6] wo m s b h 2 3 program to 3d [8] wo s pare 1 0 dont care for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com plls with i ntegrated vco - s m t 61 HMC834LP6GE v01.0112 fractional- n p ll with i ntegrated v co 45 - 1050, 1400 - 2100, 2800 - 4200, 5600 - 8400 m h z note s: for price, delivery and to place orders: hittite microwave corporation, 2 elizabeth drive, chelmsford, ma 01824 phone: 978-250-3343 fax: 978-250-3373 order on-line at www.hittite.com application support: phone: 978-250-3343 or apps@hittite.com |
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